Abstract-This work presents a fast and flexible framework for congestion analysis at the global routing stage. It captures various factors that contribute to congestion in modern designs. The framework is a practical realization of a proposed parameterized integer programming formulation. The formulation minimizes overflow inside a set of regions covering the layout which is defined by an input resolution parameter. A resolution lower than the global routing grid-graph creates regions that are larger in size than the global-cells. The maximum resolution case simplifies the formulation to minimizing the total overflow which has been traditionally used as a metric to evaluate routability. A novel contribution of this work is to demonstrate that for a small analysis time budget, regional minimization of overflow with a lower resolution allows a more accurate identification of the routing congestion hotspot locations, compared to minimizing the total overflow. It allows generating a more accurate congestion heatmap. The other contributions include several new ideas for a practical realization of the formulation for industrysized benchmark instances some of which are also improvements to existing global routing procedures. This work also describes coalesCgrip, a simpler variation of our framework which was used to evaluate the ISPD 2011 contest.
Abstract-Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window,which is used to analyze logic errors during post-silicon validation. Due to limitation in the bandwidth of trace buffers, only few state elements can be selected for tracing. In this work we first propose two improvements to existing "signal selection" algorithms to further increase the logic restorability inside the chip. In addition, we observe that different selections of trace signals can result in the same quality, measured as a logic visibility metric. Based on this observation, we propose a procedure which biases the selection to increase the restorability of a desired set of critical state elements, without sacrificing the (overall) logic visibility. We propose to select the critical state elements to increase the "timing visibility" inside the chip to facilitate the debugging of timing errors which are perhaps the most challenging type of error to debug at the post-silicon stage. Specifically, we introduce a case when the critical state elements are selected to track the transient fluctuations in the power delivery network which can cause significant variations in the delays of the speedpaths in the circuit in nanometer technologies. This paper proposes to use the trace buffer technology to increase the timing visibility inside the chip, without sacrificing the logic visibility. I. INTRODUCTIONPost-silicon validation of VLSI chips has become significantly time-consuming in nanometer technologies and impacting the product time-to-market. Due to the high complexity of modern day electronic systems, logic bugs may escape the pre-silicon validation stage. However, at this stage, the lack of visibility to the signals inside the chip makes the validation a cumbersome task.Trace buffer technology has been recently used in order to track few internal state elements (i.e., signals) during the operation of a chip. These signals are selected for tracing at the design stage and the traces are analyzed at the post-silicon stage to debug logic errors. Many recent works have focused on the trace selection problem in order to maximize the chip logic visibility [4], [5], [6], where visibility is the metric used to reflect the degree of restoring the remaining state elements in the chip using the selected trace signals.In this work, we first present two enhancements to the existing trace selection algorithms:1. During computation of the visibility corresponding to a set of candidate trace signals, we show the ordering of state elements is very important. We discuss an ordering which results in more accurate computation of visibility during trace selection. 2. We propose a Pareto-algebriac procedure which in effect defers the selection of multiple trace signals, compared to existing greedy techniques which select one trace at each step. As a result, we can obtain a solution of higher visibility. Furthermore, we observe that due to the limited bandwidth of the trace buffer, many alternat...
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