Capacitance enhancement techniques for sub-100 nm trench DRAMs

Gutsche, M.; Seidl, H.; Luetzen, J.; Birner, A.; Hecht, T.; Jakschik, S.; Kerber, M.; Leonhardt, M.; Moll, P.; Pompl, T.; Reisinger, H.; Rongen, S.; Saenger, A.; Schroeder, Uwe; Sell, B.; Wahl, A.J.; Schumann, D.

doi:10.1109/iedm.2001.979524

Cited by 26 publications

(22 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The push for dielectric layers exhibiting high conformality, uniform stoichiometry and thickness, large breakdown fields, and high dielectric constants has motivated a search for alternatives to SiO 2 and associated deposition techniques [1,2]. Chemical vapor deposition (CVD) provides highly uniform films on the wafer scale but requires high growth temperatures, which can damage underlying layers as well as polymer resists [3].…”

mentioning

confidence: 99%

Low-temperature atomic-layer-deposition lift-off method for microelectronic and nanoelectronic applications

Biercuk

Monsma

Marcus

et al. 2003

Applied Physics Letters

180

142

View full text Add to dashboard Cite

We report a novel method for depositing patterned dielectric layers with submicron features using atomic layer deposition (ALD). The patterned films are superior to sputtered or evaporated films in continuity, smoothness, conformality, and minimum feature size. Films were deposited at 100-150 C using several different precursors and patterned using either PMMA or photoresist. The low deposition temperature permits uniform film growth without significant outgassing or hardbaking of resist layers. A liftoff technique presented here gives sharp step edges with edge roughness as low as 10 nm. We also measure dielectric constants (k) and breakdown fields for the high-k materials aluminum oxide (k ~ 8-9), hafnium oxide (k ~ 16-19) and zirconium oxide (k 20-29), grown under similar low temperature conditions.

show abstract

mentioning

confidence: 99%

Low-temperature atomic-layer-deposition lift-off method for microelectronic and nanoelectronic applications

Biercuk

Monsma

Marcus

et al. 2003

Applied Physics Letters

180

142

View full text Add to dashboard Cite

show abstract

“…Earlier reports of conformal coating by ALD include a paper on dynamic random access memory ͑DRAM͒ trench capacitors with ϳ100 nm wide openings and re-entrant profile ͑"bottlelike"͒ features of 50:1 aspect ratio coated with 45 Å Al 2 O 3 . 5 ALD has also been used to coat the inside surfaces of pores as small as 7 nm in diameter. 6 Because the supply of reactive molecules to the inside surfaces of a slot or trench/hole is limited by molecular diffusion, the precursor partial pressure P and the required exposure time t together determine the exposure Pt needed to achieve a saturation density ͑number of atoms/cm 2 ͒ on these surfaces.…”

Section: Resultsmentioning

confidence: 99%

ALD Refill of Nanometer-Scale Gaps with High-κ Dielectric for Advanced CMOS Technologies

Lee¹,

Seidel²,

Dalton³

et al. 2007

Electrochem. Solid-State Lett.

View full text Add to dashboard Cite

Atomic layer deposition ͑ALD͒ is demonstrated to be effective for filling gaps as small as ϳ3 nm and aspect ratios greater than 10 with no void defects. Thus, it is a promising technique to enable the fabrication of complementary metal oxide semiconductor ͑CMOS͒ transistors using a "gate-dielectric-last" process to minimize thermal exposure of the high-gate dielectric, in order to avoid issues such as gate Fermi-level pinning and increased leakage current density associated with oxygen vacancy formation and crystallization.As bulk-Si metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ are scaled down to sub-30 nm gate lengths, highpermittivity ͑high-͒ gate dielectric materials are needed in order to suppress gate leakage while providing for strong capacitive coupling between the gate and the channel to suppress detrimental shortchannel effects such as drain-induced barrier lowering ͑DIBL͒. 1 Candidate high-gate materials include aluminum oxide, hafnium silicates, and hafnium dioxide. Integration of these materials into a complementary MOS ͑CMOS͒ fabrication process presents challenges due to formation of oxygen vacancies 2 and/or crystallization, 3 which results in increased leakage current density and pinning of the effective gate work function upon exposure to significant thermal processing. Because high-temperature annealing is required to activate implanted dopants in the source and drain regions of a MOSFET, it would be advantageous to deposit the high-gate dielectric material after source/drain formation to avoid the aforementioned issues. One approach is to use a sacrificial gate-dielectric material, e.g., silicon dioxide ͑SiO 2 ͒, to form the gate stack and self-aligned source/drain regions, as in a conventional "gate-first" integrated process flow. Afterwards, the sacrificial dielectric is selectively removed from underneath the gate electrode, e.g., with a hydrofluoric ͑HF͒ vapor etch process, and then the resultant gap is refilled with high-gate dielectric material. ͑Because the gate electrode is typically much wider in the electrical contact region͑s͒ over the field oxide, it remains anchored so that liftoff of the gate electrode is avoided.͒ In future CMOS technologies employing high-gate dielectrics, the equivalent oxide thickness of the gate dielectric is typically less than 2 nm, so that the physical thickness of the high-gate dielectric layer is less than ϳ10 nm ͑depending on the dielectric constant, ͒. Thus, for the proposed gate-dielectric-last process outlined above, it would be necessary to fill nanometer-scale gaps. A highly conformal deposition process is required for the fill process to avoid the formation of "keyhole" void defects, which would reduce the effective permittivity of the gate dielectric. The technique of atomic layer deposition ͑ALD͒ is well suited to meet this critical requirement, because it can deposit material one monolayer at a time. In this paper, we explore the filling of nanometer-scale gaps ͑"nanogaps"͒ by ALD of high-material ͑Al 2 O 3 , Х 9.5͒. The gaps ar...

show abstract

“…By taking into account the added interfacial layer, the XRR fitted dielectric thicknesses are also quite similar to the values previously measured by ellipsometry. Moreover, the calculated film densities of 3.1 g/cm 3 Device characterization.-As previously mentioned, treated III-V semiconductor surfaces are usually encapsulated with dielectric films using CVD-based techniques to improve their stability. Although novel oxides and deposition techniques have been developed, PECVD deposited SiO 2 and SiN x , remained, so far, the dielectrics of choice for most applications in the III-V based microelectronic industry.…”

Section: Film Properties Of Thermal-ald-al 2 O 3 and Plasma-ald-al mentioning

confidence: 99%

Atomic Layer Deposition of Aluminum Oxide for Surface Passivation of InGaAs∕InP Heterojunction Bipolar Transistors

Driad

Benkhelifa

Kirste

et al. 2011

J. Electrochem. Soc.

View full text Add to dashboard Cite

In this paper, the growth and material properties of Al 2 O 3 layers grown by thermal atomic layer deposition (ALD) with water vapor, and plasma ALD with oxygen plasma are examined by spectroscopic ellipsometry and X-ray reflectivity on Si substrates and InGaAs/InP epilayers. The thermal-ALD and plasma-ALD deposited Al 2 O 3 layers have subsequently been used to passivate the surface of InGaAs/InP heterojunction bipolar transistors (HBTs). The impact and efficiency of the ALD-Al 2 O 3 passivation layers have been evaluated using the dc current gain and breakdown voltage of the InGaAs/InP HBTs. For comparison, the results from these experiments are contrasted with results from similar samples passivated with SiO 2 using conventional plasma enhanced chemical vapor deposition (PECVD). The thermal-ALD-Al 2 O 3 passivated InGaAs/InP HBTs show higher current gains as compared to structures passivated using the plasma-ALD or PECVD processes, suggesting differences in the dielectric-semiconductor interface properties. More importantly, as compared to PECVD-SiO 2 , the common emitter characteristics of both (thermal and plasma) ALD-Al 2 O 3 passivated HBTs show fairly stable device breakdown voltage, which is of particular importance, especially in analog applications.

show abstract

Capacitance enhancement techniques for sub-100 nm trench DRAMs

Cited by 26 publications

References 1 publication

Low-temperature atomic-layer-deposition lift-off method for microelectronic and nanoelectronic applications

Low-temperature atomic-layer-deposition lift-off method for microelectronic and nanoelectronic applications

ALD Refill of Nanometer-Scale Gaps with High-κ Dielectric for Advanced CMOS Technologies

Atomic Layer Deposition of Aluminum Oxide for Surface Passivation of InGaAs∕InP Heterojunction Bipolar Transistors

Contact Info

Product

Resources

About