No abstract

No abstract

Essential techniques that allow W h e r scaling of trench DRAMs beyond 100 nm have been developed. (1) A1203 was implemented as high-k node dielectric in silicon-insulatorsilicon trench capacitors. A1203 films were deposited by ALD with excellent step coverage at aspect ratios of up to AR --60. Even.after thermal stressing at 1050 "C an effective oxide thickness ( = capacitance equivalent thickness) of to, = 3.6 nm and a leakage current of well below 1 fA/cell were obtained. (2) Both selective and non-selective HSG Si was formed inside high-aspect ratio straight and bottled trenches. On fully integrated 0.17 pm trench DRAMs, a storage capacitance of 45 fF/cell with acceptable leakage current was achieved. Both the aluminum oxide node dielectric and the HSG silicon have thus been proven to withstand the high thermal budget required for integration into trench DRAMs. (3) In addition, a silicon etch process was developed that allows trench aspect ratios of AR = 60 at critical dimensions of CD = 80 nm.

For the first time, fully integrated 128Mb trench DRAMs using A1203 as high-k node dielectric in silicon-insulatorsilicon (SIS) capacitors were successfully fabricated. A highly manufacturable integration scheme for Alz03 as node dielectric in trench capacitors was developed and successfully implemented in a 170nm ground rule technology. A capacitance close to SOfF/cell with leakage current well below IfNcell was achieved, leading to significantly improved retention characteristics. 128Mb DRAM devices with full functionality and excellent test yields were obtained. The scalability of this technology to smaller dimensions is demonstrated by the integration of ALD (Atomic Layer Deposition) AIz03 into 1 lOnm ground rule trench capacitors. In addition, trench capacitors with A1203 on hemispherical grain (HSG) silicon were fabricated, exhibiting high capacitance enhancement with low leakage current.

No abstract