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In the past years, the interest in the physics of mesoscopic device structures has increased as the patterning of such systems became more and more applicable. Mesoscopic structures uncover new physics since size effects play an important role. For patterning, self-organizing processes are promising, but they can also bear difficulties. Self-organization phenomena are, however, interesting from a physical point of view and offer cheap possibilities for production purposes. But they are not totally regular, and one process is restrained to a limited number of structures and materials. For the understanding of the electrical behavior of these mesoscopic structures, the form and the slight variation of one from the other have to be taken into account as well as the material properties. In this paper, we present an electrical characterization of carbon networks produced by a self-organizing process. The net structure consists of hexagonal basis cells with a diameter of about 1 m and the dimensions of the interconnections of about 100 nm. We find that in the temperature range from 4.2 to 150 K, the specific resistivity depends on temperature T as (T)ϰT Ϫ0.3 exp(͓T 0 /T͔ 1/p ) and the transport mechanism, therefore, is variable range hopping. For 4.2 KϽTϽ26 K, it is pϭ4 and the local activation energy scales as a (T)ϰT 3/4 . In the temperature range from 4.2 to 30 K, the current-voltage characteristics exhibit a temperature-dominated part in the low-voltage regime and a voltage-dominated part in the highvoltage regime. The first can be described according to Mott's law, whereas the second scales as (E) ϭ 1 exp(A * E n ), where A and 1 depend on temperature. A change of the factor n from 1 to 0 takes place with increasing electric field.

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We present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS) / high-k dielectric and metal-in-collar (MIC), and lowk inter-level dielectric (ILD) are demonstrated. IntroductionAs shown in a previous paper, the trench DRAM technology can be extended down to 70nm by using a [100] rotated substrate and a checkerboard trench layout (1). For the further scaling of this trench cell architecture to sub 60nm feature sizes major technology and device challenges have to be addressed: