Drastic reduction in nickel oxide (NiO) film resistivity and ionization potential is observed when subjected to ultraviolet (UV)/ozone (O) treatment. X-ray photoemission spectroscopy suggests that UV/O treatment changes the film stoichiometry by introducing Ni vacancy defects. Oxygen-rich NiO having Ni vacancy defects behaves as a p-type semiconductor. Therefore, in this work, a simple and effective technique to introduce doping in NiO is shown. Angle-resolved XPS reveals that the effect of UV/O treatment does not only alter the film surface property but also introduces oxygen-rich stoichiometry throughout the depth of the film. Finally, simple metal/interlayer/semiconductor (MIS) contacts are fabricated on p-type Si using NiO as the interlayer and different metals. Significant barrier height reduction is observed with respect to the control sample following UV/O treatment, which is in agreement with the observed reduction in film resistivity. From an energy band diagram point of view, the introduction of the UV/O treatment changes the defect state distribution, resulting in a change in the pinning of the Fermi level. Therefore, this work also shows that the Fermi level pinning property of NiO can be controlled using UV/O treatment.

An electrostatically actuated double-clamped cantilever beam test structure has been designed and fabricated to determine the adhesion forces between co-planar, impacting polycrystalline silicon (polysilicon) surfaces. To examine the effect of apparent contact area, dimples of varying sizes have been included in the test structure. By measuring the cantilever beam profile, through optical interferometric methods, as a function of applied bias, the force of adhesion has been determined for various device geometries. The results reveal a weak dependence of adhesion on apparent contact area, rather than a linear dependence. Fabrication process artifacts, observed and discussed here, contribute to but do not suffice to explain this observed weak scaling. The results strongly suggest that contact on the micrometer scale between rough, rigid materials such as polysilicon involves only a few asperities.

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Atomic layer deposition ͑ALD͒ is demonstrated to be effective for filling gaps as small as ϳ3 nm and aspect ratios greater than 10 with no void defects. Thus, it is a promising technique to enable the fabrication of complementary metal oxide semiconductor ͑CMOS͒ transistors using a "gate-dielectric-last" process to minimize thermal exposure of the high-gate dielectric, in order to avoid issues such as gate Fermi-level pinning and increased leakage current density associated with oxygen vacancy formation and crystallization.As bulk-Si metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ are scaled down to sub-30 nm gate lengths, highpermittivity ͑high-͒ gate dielectric materials are needed in order to suppress gate leakage while providing for strong capacitive coupling between the gate and the channel to suppress detrimental shortchannel effects such as drain-induced barrier lowering ͑DIBL͒. 1 Candidate high-gate materials include aluminum oxide, hafnium silicates, and hafnium dioxide. Integration of these materials into a complementary MOS ͑CMOS͒ fabrication process presents challenges due to formation of oxygen vacancies 2 and/or crystallization, 3 which results in increased leakage current density and pinning of the effective gate work function upon exposure to significant thermal processing. Because high-temperature annealing is required to activate implanted dopants in the source and drain regions of a MOSFET, it would be advantageous to deposit the high-gate dielectric material after source/drain formation to avoid the aforementioned issues. One approach is to use a sacrificial gate-dielectric material, e.g., silicon dioxide ͑SiO 2 ͒, to form the gate stack and self-aligned source/drain regions, as in a conventional "gate-first" integrated process flow. Afterwards, the sacrificial dielectric is selectively removed from underneath the gate electrode, e.g., with a hydrofluoric ͑HF͒ vapor etch process, and then the resultant gap is refilled with high-gate dielectric material. ͑Because the gate electrode is typically much wider in the electrical contact region͑s͒ over the field oxide, it remains anchored so that liftoff of the gate electrode is avoided.͒ In future CMOS technologies employing high-gate dielectrics, the equivalent oxide thickness of the gate dielectric is typically less than 2 nm, so that the physical thickness of the high-gate dielectric layer is less than ϳ10 nm ͑depending on the dielectric constant, ͒. Thus, for the proposed gate-dielectric-last process outlined above, it would be necessary to fill nanometer-scale gaps. A highly conformal deposition process is required for the fill process to avoid the formation of "keyhole" void defects, which would reduce the effective permittivity of the gate dielectric. The technique of atomic layer deposition ͑ALD͒ is well suited to meet this critical requirement, because it can deposit material one monolayer at a time. In this paper, we explore the filling of nanometer-scale gaps ͑"nanogaps"͒ by ALD of high-material ͑Al 2 O 3 , Х 9.5͒. The gaps ar...