BTI aware thermal management for reliable DVFS designs

Abstract

Abstract-In this paper, we show that dynamic voltage and frequency scaling (DVFS) designs, together with stress-induced BTI variability, exhibit high temperature-induced BTI variability, depending on their workload and operating modes. We show that the impact of temperature-induced variability on circuit lifetime can be higher than that due to stress and exceed 50% over the value estimated considering the circuit average temperature. In order to account for these variabilities in lifetime estimation at design time, we propose a simulation framework for the BTI degradation analysis of DVFS designs accounting for workload and actual temperature profiles. A profile is generated considering statistically probable workload and thermal management constraints by means of the HotSpot tool. Using the proposed framework we explore the expected lifetime of the ethernet circuit from the IWLS05 benchmark suite, synthesized with a 32nm CMOS technology library, for various thermal management constraints. We show that margin-based design can underestimate or overestimate lifetime of DVFS designs by up to 67.8% and 61.9%, respectively. Therefore, the proposed framework allows designers to select appropriately the dynamic thermal management constraints in order to tradeoff long-term reliability (lifetime) and performance with upto 35.8% and 26.3% higher accuracy, respectively, against a temperature-variability unaware BTI analysis.

Task Scheduling Frameworks for Heterogeneous Computing Toward Exascale

“…This provides concurrent use of CPU and GPU to carry out the application threads, but in [67,69], a static dividing is performed by using all the CPU and GPU cores. Researchers of [68] established that the influence of temperature-induced variability on circuit lifetime can be elevated due to stress and exceed over the value estimated bearing in mind the circuit average temperature. The researcher presents a simulation framework for the BTI degradation analysis of DVFS designs that considers thermal profiles under the Dynamic Thermal Management (DTM) system influence.…”

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

“…In this regard, actual thermal profiles of the memory can be derived by means of the HotSpot tool [35], provided that information on the workload are available. If the actual workload is not known at design time, the statistically probable workload can be selected, as proposed in [36]. Afterwards, the considered metrics are evaluated by HSPICE simulations allowing designers to explore different trade-offs between power consumption and reliability.…”

“…As highlighted in Section III, BTI aging depends considerably on utilization and temperature, which therefore affect the trend over time of static power consumption, SER and SNM. Moreover, these metrics can also be affected by process variations, as we will show in Section VI-D. At design time, information on the workload can allow designers to build up a thermal map of the ICs with the temperature distribution [36]. Moreover, the impact of process variations can also be estimated at design time.…”

Reliable mapping and partitioning of performance-constrained openCL applications on CPU-GPU MPSoCs

“…The Authors in [6] show that the impact of temperature-induced variability on circuit lifetime can be higher due to stress and exceed over the value estimated considering the circuit average temperature. They propose a simulation framework for the BTI degradation analysis of DVFS designs that considers thermal profiles under the influence of a Dynamic Thermal Management (DTM) system.…”

“…Scaling to new technology nodes leads to progressive degradation of the performance characteristics of devices and system components [7] induced by aging phenomena. Some works show that the impact of temperature-induced variability on circuit lifetime can be higher than that due to stress and exceed 50% over the value estimated considering the circuit average temperature [6].…”