Task Scheduling Frameworks for Heterogeneous Computing Toward Exascale

Abstract

The race for Exascale Computing has naturally led computer architecture to transit from the multicore era and into the heterogeneous era. Many systems are shipped with integrated CPUs and graphics processing units (GPUs). Moreover, various applications need to utilize both CPUs and GPUs executive resources, as many of their unique features prove the significant importance and strengths of using each one of the process units PUs. Several research studies consider partitioning the applications, scheduling their execution and allocating them onto the PUs resources. They investigate the important role of optimization and tackle intelligently scheduled tasks on the combination of CPU/GPU architecture CPUs and GPUs cores in achieving the peace of performance and power consumption of Exascale Computing. In this paper, the evolution of heterogeneous computing architectures, the approaches, and challenges toward achieving Exascale Computing, and the various algorithms and techniques used to partition and scheduling tasks are all reviewed. The existing frameworks and runtime systems utilized to optimize performance and improve energy efficiency in desecrates and fused chips in order to attain the objectives of Exascale Computing will also be reviewed.

Communication and Computation Aware Task Scheduling Framework Toward Exascale Computing

“…In 2013, Titan in the USA and Tsubame KFC Tokyo Tech were the biggest supercomputers. They were 2.5GFlops/W and 4.5GFlops/W, respectively [3] in time they both use heterogeneous computing, as both were utilizing K20 GPU, but Tsubame KFC have several advantages on Titan.…”

“…Thus, one way of thinking to reach exascale is the improvements that are 20PFlops, 10Wand 107threads so as by 2023, it will have been duplicated 50times to get 1000GFlops besides only duplicating the power consumption twice. Hence, power efficiency must go up to 25 times of the 2013 range [3]. This efficiency is derived from process technology, better hardware and software architecture and circuits, in addition to utilizing, parallelize and improving the thread from 10 7 to 10 10 [3,4].…”

“…Hence, power efficiency must go up to 25 times of the 2013 range [3]. This efficiency is derived from process technology, better hardware and software architecture and circuits, in addition to utilizing, parallelize and improving the thread from 10 7 to 10 10 [3,4].…”

“…This way, we can benefit from the advantages of each and leverage the intelligent combination of both so as to achieve exascale performance and power consumption. Heterogeneous computing systems (HCS) are considered by many researchers the Exascale Computing system outrigger [3,4]. In an HCS, a various types of computing nodes, that are characterized by unrelated capabilities and equipped with spectrum types of computation units, are all interconnected via a highspeed network.…”

“…The efficient scheduling framework is capable of partitioning a job into small tasks, scheduling them on the HCS processing units in an efficiency way which achieves the minimum time-span and uses resources efficiently, in order for the job to be executed [3,4]. Mapping the tasks into the best-fit computing resources is the aim of task scheduling and allocating algorithms.…”