Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

Meijer, Maurice; Gyvez, José Pineda de

doi:10.1109/tvlsi.2010.2091974

Cited by 24 publications

(13 citation statements)

References 17 publications

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“…Hence, SMA-SSTA significantly improves the area efficiency (by 1.63×), compared with traditional corner-based timing analysis. The joint adoption of SFBB and SMA-SSTA enables for the first time variation-aware body-biased design, as opposed to previous body-biasing design strategies that either completely ignore variations [11]- [13], or suffer from large guardband due to the simplistic timing analysis based on corners [14], [15].…”

Section: Discussionmentioning

confidence: 99%

“…Since these works do not include body-biasing information during technology mapping, the gate strength and hence area are largely oversized. To partially limit such large area penalty, the works in [14] and [15] include some limited body-biasing information based on the corner analysis. However, these frameworks are still largely pessimistic since they are based on corner and DSTA analysis.…”

Section: B Ulv Body-biasing Challengesmentioning

confidence: 99%

“…The joint adoption of the two techniques permits to go well-beyond traditional body-biasing schemes that need substantial design margins to accommodate for process variations, since they ignore the impact of body biasing at design time [11]- [13], or incorporate limited information based on corner analysis [14], [15]. As an additional benefit, the two proposed techniques synergistically reduce the silicon area for a given performance target, thanks to the gate size reduction enabled by the performance boost with SFBB and the design margin reduction with SMA-SSTA.…”

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confidence: 99%

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Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Zhao

Alioto

2015

IEEE Trans. VLSI Syst.

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Near-threshold operation enables high energy efficiency, but requires proper design techniques to deal with performance loss and increased sensitivity to process variations. In this paper, we address both issues with two synergistic approaches. First, we introduce a novel body-biasing technique to mitigate the performance loss at near-threshold voltages while not requiring any additional circuitry for the body-bias control, thereby minimizing the design effort and simplifying the systems-on-chip integration. Second, we introduce a novel statistical design methodology to efficiently and accurately evaluate the design guardband strictly needed in the worst case, thereby keeping the area cost of variations at its very minimum. A 65-nm advanced encryption standard testchip demonstrates 1.65× throughput improvement over a baseline design without body biasing, and enables reliable operation over a wide voltage range (0.5-1.2 V) as opposed to traditional body-biasing schemes. In addition, our testchip achieves 1.63× area efficiency improvement compared with a design based on corner analysis. Accordingly, the proposed techniques are well suited for the design of near-threshold specialized hardware with improved performance, reduced silicon area, and design effort.Index Terms-Advanced encryption standard (AES), energy efficiency, forward body-biasing, near-threshold VLSI circuits, process variations, statistical static timing analysis (SSTA), surrogate timing model.

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Section: Discussionmentioning

confidence: 99%

Section: B Ulv Body-biasing Challengesmentioning

confidence: 99%

mentioning

confidence: 99%

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Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Zhao

Alioto

2015

IEEE Trans. VLSI Syst.

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“…In order to increase speed and robustness against process and temperature variations while maintaining high levels of energy efficiency, the forward body biasing (FBB) technique is widely adopted [8,9,[13][14][15][16]. Because of the exponential dependence of subthreshold current on body biasing, such a technique is particularly effective in reducing circuit delay without large penalties in terms of total energy consumption [13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Albano

Lanuzza

Taco

et al. 2014

Circuit Theory & Apps

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Summary Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically examined with the main purpose of furnishing important guidelines to design efficient subthreshold digital circuits. Our modeling has been fully validated by comparing the predicted results with SPICE simulations performed for a commercial 45‐nm complementary metal oxide semiconductor technology. Considering process, temperature and loading capacitance variations, the delay of an inverter is predicted with a maximum error lower than 16.5%. Even better results are obtained when our modeling is applied to more complex logic gates. Under process, loading capacitance and temperature variations, the delay of NAND2 and NOR2 logic gates is always predicted with an error below 10%. Good agreement between the predicted and simulated results makes our modeling a valuable support during the circuit design phase. Copyright © 2014 John Wiley & Sons, Ltd.

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“…Although Nikolic et al's SAFF [7] has symmetric delay and large driving capability, its power dissipation is not so satisfactory. The power dissipation and delay of Strollo et al 's SAFF [8] is low and small, but the sum of the widths and PDP can still be improved.The bulk-driven schematic benefits CMOS digital circuits for both leakage power reduction and switching speed improvement [9,10]. However, the efficiency of bulk-driven strongly depends on the device type and operating temperature.…”

mentioning

confidence: 99%

Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range

Deng¹,

Mo²

2015

Electron. lett.

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A new boost bulk-driven sense-amplifier-based flip-flop (BBDSAFF) is presented. First, thanks to the boost and bulk-driven technique, the BBDSAFF consumes much lower power and can operate normally in the ultra-wide voltage range. Secondly, the adopted pseudo-PMOS dynamic technique in the RS latch output stage can greatly reduce the delay and improve the driving capability. The simulation results show advantages of high-speed, low power dissipation and very small and symmetrical rise/fall delay. Under the same simulation conditions, power dissipation, delay and PDP of the Strollo sense-amplifier-based flip-flop is 31 μW, 107 ps and 3.32 fJ whereas that of the proposed bulk-driven SAFF is 29 μW, 94 ps and 2.73 fJ. This low power consumption and high-speed BBDSAFF can be applied in various fields, such as ultra-dynamic voltage scaling VLSI, circuits, low power dissipation counter-clock systems and microprocessors.Introduction: With CMOS process downscaling and the operation frequency increasing, power reduction has become an important design issue for circuits and applications. Advance microprocessors are composed of a large number of registers or flip-flops, which consume 27-60% of the total system power [1]. Recently, ultra-dynamic voltage scaling (UDVS) has become the most efficient approach for reducing power consumption [2]. Generally, the optimal supply voltage for a given process and the threshold voltage depends on both logic style and logic functions to be implemented, but the optimal supply voltage for all digital implementations will be significantly lower than the allowed supply voltage for that process. Voltage scaling reduces the active energy and unfortunately the speed as well [3]. So far, the UDVS technology is only applied to combinational logic circuits. All the registers or flipflops in the UDVS systems work at the allowed supply voltage for the process. For UDVS VLSI it is crucial to design a low-power high-speed flip-flop operating in the ultra-wide voltage range.A lot of research has been carried out to improve the performance of flip-flops [4,5]. Gao et al. [4] proposed a novel master-slave D flip-flop and [5] presented a DCVSL flip-flop, both of which are the best candidates for high-speed applications but require a higher supply voltage and have more power dissipation. The sense-amplifier-based flip-flop (SAFF) is the best choice for the ultralow-voltage technique [1]. As a result, a SAFF is usually used in memory cores and low-swing bus drivers to improve performance or reduce power dissipation. Several high-performance SAFF structures have been proposed recently [6-8], all of which are based on the circuit conventional sense amplifier flip-flop. The one proposed by Matsui et al.[6] is characterised by a near-zero setup time, a reduced hold time, a low clock load and true single-phase operation. However, it has asymmetrical delay with a slow high-to-low delay. Although Nikolic et al.'s SAFF [7] has symmetric delay and large driving capability, its power dissipation is not so satisfactory. ...

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Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

Cited by 24 publications

References 17 publications

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range

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