Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Very large scale integration (VLSI)-based neuromorphic systems have been evolving quickly in recent years. These systems have been used in complex cognitive tasks such as image classification and pattern recognition. A neuromorphic encoder is an essential component in a neuromorphic system, which converts sensory data into spike trains. The advancement in CMOS technology nodes leads to various reliability issues. Bias temperature instability (BTI) and hot carrier injection (HCI) are major reliability issues in analog/ mixed VLSI circuits. This paper implements a temporal neuromorphic encoder, and a corresponding mathematical model is derived for image processing applications. The relationship between an input image pixel value and output of the encoder, that is, interspike interval (ISI), is found to be exponential. The impact of BTI and HCI on the temporal neuromorphic encoder is analyzed. The degradation analysis revealed a loss of encoding functionality for which three mitigation techniques are discussed. Finally, a reliability-aware neuromorphic encoder is proposed to minimize the effect of degradation over its lifetime. The power consumption of conventional and proposed reliabilityaware neuromorphic encoders is also presented.

“…The transistors are held in the subthreshold region such that the input current ( I IN ) flowing through PM4 exhibit an exponential relation with the V IN as given in Equation 2. 37

I_{IN} goodbreak= I_{0} \exp ((), \frac{V_{normalX} - V_{IN} - ∣ V_{THp} ∣}{s . U_{normalT}}),

where V X is the potential at node x , | V THp | is the threshold voltage of PM4, s is the subthreshold slope, U T is the thermal voltage, and I 0 is the subthreshold saturation current.…”

Section: Mathematical Model Of Neuromorphic Encoder For Image Processingmentioning

confidence: 99%

Reliability‐aware design of temporal neuromorphic encoder for image recognition

Shaik

Singhal

et al. 2021

“…In this work, a compact and simple solution for silicon-based static PUFs, based on two-transistor (2T) voltage dividers (Figure 1), is presented. The 2T voltage divider exploits subthreshold operation [22][23][24][25][26][27] to emphasize the random process fluctuations. Therefore, thanks to its high variability, the proposed PUF solution exhibits high robustness against noise, supply voltage, and temperature variations.…”

Section: Introductionmentioning

confidence: 99%

A physical unclonable function based on a 2‐transistor subthreshold voltage divider

Rose

Crupi

Lanuzza

et al. 2016

In this paper, a compact circuit solution for silicon-based static physical unclonable functions (PUFs) is presented. The proposed solution exploits the variability of a simple voltage divider, implemented by two identical series-connected nMOSFETs in a commercial 65-nm CMOS process, to generate a random and stable nanokey. Both the transistors are biased in the subthreshold regime to enhance the output voltage dispersion and consequently the variability of the PUF response. The bit key generation is obtained by comparing the analog outputs of a pair of voltage dividers. Monte Carlo simulations on 10,000 samples have been performed to deduce the design guidelines for transistor sizing aimed at ensuring a high robustness of the PUF response against noise, supply voltage, and temperature variations. When compared with some state-of-the-art PUF designs, the proposed circuit solution proves to be a promising and competitive candidate for implementing analog and static PUFs featuring small area occupancy, low-power features, and high reliability. Figure 9. Temperature bit-flipping (bf T ) as a function of transistor channel (right) width (W) and (left) length (L) at V DD = 1V. [Colour figure can be viewed at wileyonlinelibrary.com]

“…Power consumption arises from two main sources: dynamic power related to the circuit switching activity and static power that is exacerbated from the increased leakage current as a consequence of reduced threshold voltage of the transistors in advanced nanoscale process technologies . Voltage scaling is well known to be an effective way to reduce dynamic power consumption of an integrated circuit . However, due to the degraded performance and robustness issues, the voltage scaling technique is often applied in a selective way in multi‐supply voltage designs where some sections run at the nominal supply voltage ( V DDH ) to maximize the speed and/or to assure reliable operation , whereas noncritical sections can operate at lower supply voltage ( V DDL ) to optimize energy consumption.…”

Section: Introductionmentioning

confidence: 99%

Low energy/delay overhead level shifter for wide‐range voltage conversion

Lanuzza

Crupi

Rao

et al. 2016

Multi-supply voltage systems on chip have been widely explored for energy-efficient elaborations. A main challenge of multi-supply voltage designs is the interfacing of digital signals coming from ultra-low-voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay-efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single-stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull-up network on the basis of the occurring transition. A test chip was fabricated in 180 nm complementary metal–oxide–semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100 mV of input voltages to 1.8 V, while assuring an average propagation delay of about 26 ns, an average static power of 100 pW, and an energy per transition of 140 fJ for the target voltage-level conversion from 0.4 to 1.8 V