Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Abstract

Near-threshold operation enables high energy efficiency, but requires proper design techniques to deal with performance loss and increased sensitivity to process variations. In this paper, we address both issues with two synergistic approaches. First, we introduce a novel body-biasing technique to mitigate the performance loss at near-threshold voltages while not requiring any additional circuitry for the body-bias control, thereby minimizing the design effort and simplifying the systems-on-chip integration. Second, we introduce a novel statistical design methodology to efficiently and accurately evaluate the design guardband strictly needed in the worst case, thereby keeping the area cost of variations at its very minimum. A 65-nm advanced encryption standard testchip demonstrates 1.65× throughput improvement over a baseline design without body biasing, and enables reliable operation over a wide voltage range (0.5-1.2 V) as opposed to traditional body-biasing schemes. In addition, our testchip achieves 1.63× area efficiency improvement compared with a design based on corner analysis. Accordingly, the proposed techniques are well suited for the design of near-threshold specialized hardware with improved performance, reduced silicon area, and design effort.Index Terms-Advanced encryption standard (AES), energy efficiency, forward body-biasing, near-threshold VLSI circuits, process variations, statistical static timing analysis (SSTA), surrogate timing model.

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

“…Only a few IoT-oriented commercial AES controllers are available; an example is the Maxim MAXQ1061 [14], claiming up to 20 Mbit/s (power consumption data is not currently disclosed). Research AES accelerators in the sub-100 mW range for the IoT domain have been proposed by Mathew et al [15] in Intel 22nm technology, Zhang et al [16] in TSMC 40 nm and Zhao et al [17] in 65 nm; the latter reaches efficiency up to 620 Gbit/s/W thanks to efficient body biasing and a statistical design flow targeted at reducing worst-case guard bands. A device consuming as little as 0.25 µW for passive RFID encryption has been proposed by Hocquet et al [18].…”