Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range

Abstract

A new boost bulk-driven sense-amplifier-based flip-flop (BBDSAFF) is presented. First, thanks to the boost and bulk-driven technique, the BBDSAFF consumes much lower power and can operate normally in the ultra-wide voltage range. Secondly, the adopted pseudo-PMOS dynamic technique in the RS latch output stage can greatly reduce the delay and improve the driving capability. The simulation results show advantages of high-speed, low power dissipation and very small and symmetrical rise/fall delay. Under the same simulation conditions, power dissipation, delay and PDP of the Strollo sense-amplifier-based flip-flop is 31 μW, 107 ps and 3.32 fJ whereas that of the proposed bulk-driven SAFF is 29 μW, 94 ps and 2.73 fJ. This low power consumption and high-speed BBDSAFF can be applied in various fields, such as ultra-dynamic voltage scaling VLSI, circuits, low power dissipation counter-clock systems and microprocessors.Introduction: With CMOS process downscaling and the operation frequency increasing, power reduction has become an important design issue for circuits and applications. Advance microprocessors are composed of a large number of registers or flip-flops, which consume 27-60% of the total system power [1]. Recently, ultra-dynamic voltage scaling (UDVS) has become the most efficient approach for reducing power consumption [2]. Generally, the optimal supply voltage for a given process and the threshold voltage depends on both logic style and logic functions to be implemented, but the optimal supply voltage for all digital implementations will be significantly lower than the allowed supply voltage for that process. Voltage scaling reduces the active energy and unfortunately the speed as well [3]. So far, the UDVS technology is only applied to combinational logic circuits. All the registers or flipflops in the UDVS systems work at the allowed supply voltage for the process. For UDVS VLSI it is crucial to design a low-power high-speed flip-flop operating in the ultra-wide voltage range.A lot of research has been carried out to improve the performance of flip-flops [4,5]. Gao et al. [4] proposed a novel master-slave D flip-flop and [5] presented a DCVSL flip-flop, both of which are the best candidates for high-speed applications but require a higher supply voltage and have more power dissipation. The sense-amplifier-based flip-flop (SAFF) is the best choice for the ultralow-voltage technique [1]. As a result, a SAFF is usually used in memory cores and low-swing bus drivers to improve performance or reduce power dissipation. Several high-performance SAFF structures have been proposed recently [6-8], all of which are based on the circuit conventional sense amplifier flip-flop. The one proposed by Matsui et al.[6] is characterised by a near-zero setup time, a reduced hold time, a low clock load and true single-phase operation. However, it has asymmetrical delay with a slow high-to-low delay. Although Nikolic et al.'s SAFF [7] has symmetric delay and large driving capability, its power dissipation is not so satisfactory. ...

Wide‐input dynamic range 1 MHz clock ultra‐low supply flip‐flop

“…The asymmetrical C-Q of conventional SAFF was overcome in Nikolic SAFF [5] and Strollo SAFF [6] by utilising a symmetrical slave latch. There are also other recently proposed improved SAFF topologies namely boost-bulk SAFF (BB-SAFF) [7] and transition completion detection SAFF (TCD-SAFF) [8]. Nevertheless, all these SAFF topologies still suffer from poor driving capability at ultra-low supply voltages leading to speed degradation and poor PDP performance.…”

“…Simulation results: The proposed CB-SAFF has been designed in 40 nm CMOS along with the conventional SAFF [4], Nikolic SAFF [5], recently proposed BB-SAFF [7] and TCD-SAFF [8] for evaluation of performance metrics in same environment. All SAFFs are individually optimised, use same size input/output transistors and load capacitance of 15 fF for fair comparison.…”

Investigation and design of low power circuit blocks for medical implant SOCs

“…The proposed capacitively boosted SAFF is designed using 40 nm / 1.1 V CMOS technology. Other SAFF topologies such as the recently published BB-SAFF [39] and TCD-SAFF [40], Nikolic SAFF [37] and conventional SAFF [36] are also designed in 40 From the simulation results, it can be observed that the proposed CB-SAFF achieves the lowest power-delay product among all the other SAFF topologies for a VDD of 0.16 V to 0.6 V. The proposed FF is also the only flip-flop which can work at a VDD of 0.16 V at a CLK of 1 MHz as shown in Figure 3.3. The supply voltage is kept below 0.7 V, to prevent the parasitic junction diodes from forward biasing which will increase the overall power consumption.…”

“…Another SAFF topology which achieved low propagation delay than [28] also suffered from larger asymmetrical delays at ultra-low supply voltages due to poor drive strength [38] as shown in Figure 2.6. Recently, other improved performance SAFF topologies such as the boost-bulk SAFF (BBSAFF) [39] as shown in Figure 2.7 and the transition completion detection SAFF (TCD-SAFF) [40] as shown in Figure 2.8 were proposed and they also suffer from larger asymmetrical delays due to a greater imbalance between their output charging and discharging paths.…”