A new boost bulk-driven sense-amplifier-based flip-flop (BBDSAFF) is presented. First, thanks to the boost and bulk-driven technique, the BBDSAFF consumes much lower power and can operate normally in the ultra-wide voltage range. Secondly, the adopted pseudo-PMOS dynamic technique in the RS latch output stage can greatly reduce the delay and improve the driving capability. The simulation results show advantages of high-speed, low power dissipation and very small and symmetrical rise/fall delay. Under the same simulation conditions, power dissipation, delay and PDP of the Strollo sense-amplifier-based flip-flop is 31 μW, 107 ps and 3.32 fJ whereas that of the proposed bulk-driven SAFF is 29 μW, 94 ps and 2.73 fJ. This low power consumption and high-speed BBDSAFF can be applied in various fields, such as ultra-dynamic voltage scaling VLSI, circuits, low power dissipation counter-clock systems and microprocessors.Introduction: With CMOS process downscaling and the operation frequency increasing, power reduction has become an important design issue for circuits and applications. Advance microprocessors are composed of a large number of registers or flip-flops, which consume 27-60% of the total system power [1]. Recently, ultra-dynamic voltage scaling (UDVS) has become the most efficient approach for reducing power consumption [2]. Generally, the optimal supply voltage for a given process and the threshold voltage depends on both logic style and logic functions to be implemented, but the optimal supply voltage for all digital implementations will be significantly lower than the allowed supply voltage for that process. Voltage scaling reduces the active energy and unfortunately the speed as well [3]. So far, the UDVS technology is only applied to combinational logic circuits. All the registers or flipflops in the UDVS systems work at the allowed supply voltage for the process. For UDVS VLSI it is crucial to design a low-power high-speed flip-flop operating in the ultra-wide voltage range.A lot of research has been carried out to improve the performance of flip-flops [4,5]. Gao et al. [4] proposed a novel master-slave D flip-flop and [5] presented a DCVSL flip-flop, both of which are the best candidates for high-speed applications but require a higher supply voltage and have more power dissipation. The sense-amplifier-based flip-flop (SAFF) is the best choice for the ultralow-voltage technique [1]. As a result, a SAFF is usually used in memory cores and low-swing bus drivers to improve performance or reduce power dissipation. Several high-performance SAFF structures have been proposed recently [6-8], all of which are based on the circuit conventional sense amplifier flip-flop. The one proposed by Matsui et al.[6] is characterised by a near-zero setup time, a reduced hold time, a low clock load and true single-phase operation. However, it has asymmetrical delay with a slow high-to-low delay. Although Nikolic et al.'s SAFF [7] has symmetric delay and large driving capability, its power dissipation is not so satisfactory. ...
A new bulk-driven sense-amplifier based flip-flop (BDSAFF) is presented in this paper. Based on bulk-driven technique, this new flip-flop can reduce power dissipation by connecting control signals from the bulk terminal so as to control the substrate bias and generate current difference. The adopted pseudo-PMOS dynamic technology in the RS latch output stage can greatly reduce delay and improve driving capability. The simulation results, with respect to the recently proposed high-performance flip-flops, show advantages of high speed, low power dissipation, very small and balanced rise/fall delay. Under the same simulation conditions, the power dissipation, delay and PDP of the Strollo SAFF is 31μW, 107ps and 3.32fJ while that of the proposed BDSAFF is 29μW, 94ps and 2.73fJ. This new flip-flop can be used in memory cores and low-swing bus drivers to improve performance or reduce power dissipation.
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