A novel sense-amplifier based flip-flop with bulk-driven technique

Abstract

A new bulk-driven sense-amplifier based flip-flop (BDSAFF) is presented in this paper. Based on bulk-driven technique, this new flip-flop can reduce power dissipation by connecting control signals from the bulk terminal so as to control the substrate bias and generate current difference. The adopted pseudo-PMOS dynamic technology in the RS latch output stage can greatly reduce delay and improve driving capability. The simulation results, with respect to the recently proposed high-performance flip-flops, show advantages of high speed, low power dissipation, very small and balanced rise/fall delay. Under the same simulation conditions, the power dissipation, delay and PDP of the Strollo SAFF is 31μW, 107ps and 3.32fJ while that of the proposed BDSAFF is 29μW, 94ps and 2.73fJ. This new flip-flop can be used in memory cores and low-swing bus drivers to improve performance or reduce power dissipation.