Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS

Abstract

It is important to predict noise at the early stages of a top down design. In this papel; we propose a methodology to modelphase noise orjitter; a key specification forphaselocked loops, using a mixed-signal hardware description language, and to simulate the efects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedicated noise simulators or postpone noise and fault simulation to the transistor level, we have successfully demonstrated that noise in a voltage-controlled oscillator; power supply noise, and their effects on the overall phase jitter within a faultyphaselocked loop can be modeled and simulated earlier on at the behavioral level. Our simulation results are consistent with experimentally verified, theoretical predictions. MotivationAnalog testing, being currently performed by performance measurement, is becoming a bottleneck that affects both the cost and time-to-market of mixed-signal circuits and systems. Recently, significant progress has been made to address this challenge by using an alternate, faultdriven and simulation-based methodology [ 171. A key enabling technique is behavioral modeling -more specifically, restricted behavioral modeling, mixed behavioral and structural modeling, and induced behavioral fault modeling. Restricted behavioral modeling, or macromodeling, is to model transistor-level faults at the block-level using available circuit-level primitives. This has been demonstrated on operational amplifiers [ 16, 191 and sample-hold circuits [24]. Mixed behavioral and structural modeling is to replace fault-free blocks by their behavioral models and consider fault blocks at the transistor level. Its advantages have been demonstrated on phase-locked loops (PLLs) and *This research is sponsored by the U S Defense Advanced Research Projects Agency (DARPA) under grant number F33615-96-1-5601 from the U S . Air Force, Wright Laboratory, Manufacturing Technology Directorate. A/D converters [ 11, 14,211. Induced behavioral fault modeling is to model both fault-free and faulty blocks at the behavioral level. It has been demonstrated on PLLs [4, 231 and switched-capacitor circuits [3,4].However, an issue that has not been addressed by previous behavioral fault modeling efforts, especially AHDLbased modeling, is whether it is possible to model circuit noise at the behavioral level using analog (and mixedsignal) hardware description languages (AHDLs), and simulate the effect of faults on it. It is well known that noise modeling is a key design issue for many analog circuits, One of the most important parameters for PLL design is phase noise or jitter. For example, the available clock period of a PLL in digital design is shortened in effect by the peak-to-peak jitter [7]. Previous attempts to address this issue include [20,25], but they are based on simplified linear models and the jitter evaluation process followed is quite involved.In this paper, we propose an AHDL-based methodology for noise modeling and study how fault...

Automotive VHDL-AMS Electro-Mechanics Simulations

“…A methodology for the design of RF circuits in VHDL-AMS starting from flexible specifications and assuring an accurate description of noise and nonlinear effects was proposed in (W. Yang & Yan, 2005). In (Godambe & Shi, 1998) the real behavior of a PLL was modeled using VHDL-AMS adding jitter: the phase noise simulated spectrum was in good agreement with measured results. A top-down design methodology, validated by measurements, was proposed in (V. Nguyen & Naviner, 2005) for the design of a delta-sigma modulator.…”

Analogue and mixed-signal extension to SystemC

“…Fig. 9 shows a block diagram of a digital PLL [43], [44] in a frequency synthesizer configuration. It consists of a reference …”

Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption

“…The theoretical jitter analysis of all the main contributors to the output jitter has been done for PLL/DLL systems [6], [7]. Also, the transistor level jitter analysis has been carried out for the charge pump [8] and the voltage controlled delay line [9], [10].…”

“…However new design difficulties have arose due to this decreasing transistor dimensions [3]- [5]. As it will be demonstrated, once the delay-locked loop (DLL) architecture and size (number of cells) has been fixed, the actual dimensions of the DLL blocks have a great impact on the performance of the system.The theoretical jitter analysis of all the main contributors to the output jitter has been done for PLL/DLL systems [6], [7]. Also, the transistor level jitter analysis has been carried out for the charge pump [8] and the voltage controlled delay line [9], [10].…”