Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption

Abstract

Abstract-This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.Index Terms-DLL, CMOS, behavioural, modelling, Verilog-A, optimisation I. INTRODUCTION During the last years the scaling of the CMOS technology has allowed the integration of full systems on a chip (SoC), including both the digital and analog blocks, as well as the RF front-end [1], [2]. However new design difficulties have arose due to this decreasing transistor dimensions [3]- [5]. As it will be demonstrated, once the delay-locked loop (DLL) architecture and size (number of cells) has been fixed, the actual dimensions of the DLL blocks have a great impact on the performance of the system.The theoretical jitter analysis of all the main contributors to the output jitter has been done for PLL/DLL systems [6], [7]. Also, the transistor level jitter analysis has been carried out for the charge pump [8] and the voltage controlled delay line [9], [10]. This theoretical models have allowed to predict the jitter performance of the DLL blocks and their contribution to the total output jitter. However, their limited accuracy has led to the use of behavioural models based on transistor level simulations, for both PLLs [11] and DLLs [12]. But, even with these latter models, the task to methodically analyse the system for a wide range of dimensions is a very time consuming procedure. This prevents to obtain an accurate model for the DLL jitter performance and the power consumption.In this paper a new fast behavioural model to analyse the impact of the physical transistor dimensions on the overall performance of a DLL is developed. In section II an introduction to the main sources of jitter in a DLL is carried out, while in section III a behavioural model for the DLL blocks is developed. The basis for fast model DLL simulation are explained in section IV. Finally, the results obtained with the introduced model are analysed and discussed in section V.

Layout regularity for design and manufacturability

“…• For analog design, we have implemented the DLL design and compared it to its full custom version (FC). For the full custom version we have used the one designed by our colleague Enrique Barajas, from the Electronic Engineering Department at the Universitat Politècnica de Catalunya [70].…”

“…To evaluate the performance of the FC and VCTA designs an analysis of the Voltage Controlled Delay Line (VCDL) is carried out. In fact, analyzing just one the of the delay cells of the line is sufficient to determine the behavior of the whole DLL in terms of energy consumption and jitter [70]. The VCDL must be able to compensate for process, voltage and temperature (PVT) variations and provide a constant delay, thus an analysis of the dependence of the delay, energy and jitter with the voltage control is performed for both the FC and VCTA implementations of the delay cell.…”