Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

O’Hare, Dermot; Scanlan, Anthony; Thompson, Eric R.; Mullane, Brendan

doi:10.1109/tvlsi.2017.2763129

Cited by 5 publications

(10 citation statements)

References 21 publications

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“…Figure 11(a) shows a 1.2V 100MS/s 5-bit unary-weighted (33-level/16 CS rc slices) tri-level CS-DAC top-level architecture. The TRI-DACs FS differential output current is 2.4mA and the output nodes drive a resetting integrator gain stage in CTIP-ADC design [1]. The TRI-DAC major blocks in include the 16x CS rc slices, the bias circuit and the decoder logic, the design of which are detailed in the following sections.…”

Section: Conclusion From Analysis Of Dac Topologiesmentioning

confidence: 99%

“…H IGH performance, wide-bandwidth continuous-time ADCs (CT-ADCs) are employed in applications such as cellular/Wi-Fi, video cameras, and automotive radar. In this work, a DAC is employed in the feedforward path of continuous-time-input-pipelined ADC (CTIP-ADC) architecture [1]. The CTIP-ADC as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…CT-ADCs can perform accurate conversion of signals without the need for a large input sampling stage, however they require a highly linear low noise current-steering DAC (CS-DAC) with a linearity specification that matches or exceeds the overall ADC specification. This paper presents the analysis and design of a low-latency high-linearity CS-DAC suitable for a 12-bit, 100MS/s CTIP-ADC architecture as described in [1].…”

Section: Introductionmentioning

confidence: 99%

“…The analysis focuses on three types of DAC errors these are; random and deterministic mismatch errors due to current-source (CS rc ) mismatches [2], thermal noise contributed by the CS rc devices [3], and output-impedance related distortion due to the finite-outputimpedance of each CS rc [2]. The DAC in this work drives a resetting integrator gain stage in the CTIP-ADC [1]. The analysis omits the mismatch based timing errors [2] of the individual CS rc s, as the resetting action of the integrator gain stage of the CTIP-ADC negates the timing errors.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Mehta

O’Hare²,

O'Brien

et al. 2020

IEEE Open J. Circuits Syst.

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This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ∼ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.

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Section: Conclusion From Analysis Of Dac Topologiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Mehta

O’Hare²,

O'Brien

et al. 2020

IEEE Open J. Circuits Syst.

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“…The toplevel components of the CT-ADC are the filter, Flash-ADC (N-bit), DAC (N-bit), integrating-gain-stage and discretetime (DT) backend SAR-ADC (M-bit). The DAC in this paper is part of a project developing a 100MS/s CT-ADC [1]. In this work, the low latency specification of the DAC is required to match the signal and critical path delays to achieve the wide-bandwidth for the CT-ADC.…”

Section: Introductionmentioning

confidence: 99%

A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance

Mehta

Scanlan

Mullane

et al. 2019

2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)

Self Cite

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This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-toanalogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces outputimpedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.

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Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion

Shibata

2023

IEEE Open J. Solid-State Circuits Soc.

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The continuous-time (CT) pipelined analog-to-digital converter (ADC) is an emerging ADC architecture suitable for wide-bandwidth (BW) digitization in fully integrated receiver applications. It inherits the integration-friendly features of CT ADCs, such as inherent anti-aliasing, while achieving the wide-BW operation originating from discrete-time (DT) pipelined ADCs. In this review article, we introduce a gain-centric ADC model and apply the key criteria derived from the model to transform a DT pipelined ADC into a CT pipelined ADC. We then discuss the design considerations and essential building blocks of the CT pipelined ADC. Finally, we examine several implementations of this architecture with their highlights and challenges.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT) ADC, oversampling ADC, pipelined ADC, wideband ADC.

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Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

Cited by 5 publications

References 21 publications

Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance

Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion

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