Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Mehta, Shantanu; O’Hare, Daniel; O'Brien, Vincent; Thompson, Eric R.; Mullane, Brendan

doi:10.1109/ojcas.2020.2994838

Cited by 4 publications

(2 citation statements)

References 13 publications

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“…Also, area is the active area of the DAC. Besides, FOM 3 which compares the DACs in terms of ENOB in low frequency and high frequency, the operating frequency of the DAC and power is defined as 31 :

{FOM}_{3} goodbreak= 2^{(\frac{{SFDR}_{LF} - 1.76}{6.02})} goodbreak\times 2^{(\frac{{SFDR}_{HF} - 1.76}{6.02})} goodbreak\times \frac{f_{italicck}}{P_{total} - P_{sig}}

In which SFDR LF and SFDR HF are the SFDR of the DAC in low frequency and near Nyquist frequency, respectively. Also, P sig is the signal power of the DAC.…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

Ghasemi

Karami

2021

Circuit Theory & Apps

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This paper proposes a new 10-bit 1GS/s digital-to-analog converter (DAC). In the proposed DAC configuration, a beneficial combination of differential resistor ladder and current sources is utilized to attain a significant reduction of the number of unit current sources. Therefore, the suggested 10-bit DAC is constructed based on only 21 current sources and 64 unit resistors, which results in a considerable decrease regarding the occupied area and power consumption. Also, a modified 4-bit thermometer decoder using a low number of transistors, based on SET-RST D flip-flops (SR-DFFs), is offered to drive the unit current sources synchronously. The proposed DAC is simulated in 65-nm Complementary metal oxide semiconductor (CMOS) technology. The postlayout simulation results indicate the better integral nonlinearity (INL) and differential nonlinearity (DNL) parameters than 0.3 least significant bit (LSB) and 0.6 LSB, respectively. Based on achieved results, the proposed DAC consumes 9.31 mW using a single supply voltage of 1.2 V. Moreover, the spuriousfree dynamic range (SFDR) is above 57 dB over 600-MHz Nyquist bandwidth, by considering 0.0134 mm 2 its occupied area.

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{FOM}_{3} goodbreak= 2^{(\frac{{SFDR}_{LF} - 1.76}{6.02})} goodbreak\times 2^{(\frac{{SFDR}_{HF} - 1.76}{6.02})} goodbreak\times \frac{f_{italicck}}{P_{total} - P_{sig}}

In which SFDR LF and SFDR HF are the SFDR of the DAC in low frequency and near Nyquist frequency, respectively. Also, P sig is the signal power of the DAC.…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

Ghasemi

Karami

2021

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…Apart from amplitude and timing errors, finite-output-impedance of a unit CSrc cell degrades high-frequency SFDR performance of the DAC. Techniques in [16] detail how to improve outputimpedance related distortion performance of CS-DACs.…”

Section: Introductionmentioning

confidence: 99%

A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters

Mehta

Mullane

O'Brien

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a programmable amplitude and timing error shaping bandpass dynamicelement-matching (DEM) for Nyquist-rate D/A converters. Amplitude and timing-skew errors are shaped using two different loop-filters employed within the DEM structure. The systematic-duty-cycle errors are eliminated from the DAC spectrum using a controlled set of 'ON' transitions for any choice of the input-signal over the Nyquist band. The loop-filter order within the DEM can be selected to 2, 4 or 6 and the DAC errors can be shaped over a narrow or wide band for any choice of center-frequency. This work demonstrates that for a 12bit segmented Nyquist DAC (5T-7B), the in-band SFDR and IMD3 is ≥80dBs for the DEM configurations.

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Design of Low Power Current Steering DAC Using 45nm CMOS Technology

I G,

Hegde

et al. 2024

2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)

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Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Cited by 4 publications

References 13 publications

A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters

Design of Low Power Current Steering DAC Using 45nm CMOS Technology

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