This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ∼ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.
This paper presents a 6 th order programmable bandpass dynamic-element-matching (DEM) that shapes the static mismatch error of a Nyquist DAC for any choice of center-frequency. The mismatch error can be shaped over a narrow or wide band, and up to 20% of Fs depending on the target application. This work demonstrates that for a 12-bit Nyquist DAC (5T-7B), the lowest in-band SFDR and IMD3 is 88dB and 80dB respectively, for various configurations of the DEM. The DEM hardware is implemented onto a XILINX FPGA using the System-Generator for DSP TM tool with results obtained for 155MHz Fs.
This paper presents a programmable amplitude and timing error shaping bandpass dynamicelement-matching (DEM) for Nyquist-rate D/A converters. Amplitude and timing-skew errors are shaped using two different loop-filters employed within the DEM structure. The systematic-duty-cycle errors are eliminated from the DAC spectrum using a controlled set of 'ON' transitions for any choice of the input-signal over the Nyquist band. The loop-filter order within the DEM can be selected to 2, 4 or 6 and the DAC errors can be shaped over a narrow or wide band for any choice of center-frequency. This work demonstrates that for a 12bit segmented Nyquist DAC (5T-7B), the in-band SFDR and IMD3 is ≥80dBs for the DEM configurations.
This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-toanalogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces outputimpedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.
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