A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance

Abstract

This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-toanalogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces outputimpedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.