This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity.The proposed hybrid DPWM uses a synchronous counterbased coarse-resolution block and a DCM based fine-resolution block implementing a synchronous delay line.The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA with 9-bit resolution with a switching frequency of 1 MHz. Linearity was manually optimized using the presented technique which reduced the integral non-linearity error by 0.5 LSB.

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This paper proposes a new FPGA-based architecture for a multi-phase digital pulse width modulator (MP-DPWM). A novel fine-leading/coarse-trailing edge modulation is applied to allow the sharing of a single fine resolution block for all phases.

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This paper details the a digitally controlled isolated SMPC containing a novel bi-directional data transmission scheme The bi-directional data transmission scheme avoids the effects of opto-coupler aging, allows the use of digital control techniques and enables transmission of auxiliary data from primary-tosecondary and secondary-to primary. The complete digital controller was implemented one custom and two FPGA boards, and achieves programmable regulation over the 0-2.5V range.

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Abstract-An efficient high-speed bi-directional data transmission scheme for isolated AC-DC and DC-DC switched mode power converters is presented. The bi-directional scheme supports fast, efficient and reliable transmission of digitally encoded data across the isolation barrier and enables primary side control, allowing effective start-up and a simple interface to system controllers. Another key feature is that the bi-directional communication is independent of coupler gain and degradation and only the minimum number of couplers is required. The digital interface can also be used to transmit auxiliary signals between both sides. For test purposes, the scheme has been implemented on FPGAs and verified using a custom-built SMPC board.