FPGA-Based Digital Pulse Width Modulator With Optimized Linearity

Abstract

This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity.The proposed hybrid DPWM uses a synchronous counterbased coarse-resolution block and a DCM based fine-resolution block implementing a synchronous delay line.The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA with 9-bit resolution with a switching frequency of 1 MHz. Linearity was manually optimized using the presented technique which reduced the integral non-linearity error by 0.5 LSB.

Efficient Bi-Directional Digital Communication Scheme for Isolated Switch Mode Power Converters

“…In particular, its resolution must be higher than the ADC resolution to ensure stable regulation. This work uses a FPGA-based DPWM specifically designed for use with power converters [29].…”

Specialized Digital Signal Processor for control of multi-rail/multi-phase high switching frequency power converters

“…This provides sufficient precision for power converter control applications because of the limited range and resolution of the sampled voltage and current signals from the ADC. The resolution of the duty cycle value presented to the DPWM is also typically less than 16 bits [19][20][21]. The datapath's accumulator registers have 32-bit resolution in order to preserve accuracy between successive multiplyaccumulate operations.…”

FPGA-based high resolution synchronous digital pulse width modulator

“…Several FPGA-based solutions have also been proposed in the literature [8]- [13]. One common solution [9]- [13] is to use a coarse resolution counter-based stage plus one or several on-chip Digital Clock Manager (DCM) blocks.…”

“…One common solution [9]- [13] is to use a coarse resolution counter-based stage plus one or several on-chip Digital Clock Manager (DCM) blocks. The PWM signal is set at the beginning of the counter period, and it is reset after a given number of clock cycles plus a certain fraction of the clock period established by the DCM.…”