Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis

Boulé, Marc; Chenard, J.-S.; Žilić, Željko

doi:10.1109/isqed.2007.38

Cited by 54 publications

(28 citation statements)

References 7 publications

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“…Finally, ForEVeR's detection mechanism relies on the use of router-level runtime monitors, when formal methods fail to ensure router correctness. The idea of using runtime checkers has been proposed for various purposes [7,16]. [7] champions the use of runtime monitors for postsilicon debug and in-field diagnosis, as a general design methodology, while ForEVeR leverages a set of specialized hardware monitors coupled with dedicated network recovery support.…”

Section: Related Workmentioning

confidence: 99%

Formally enhanced runtime verification to ensure NoC functional correctness

Parikh

Bertacco

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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As silicon technology scales, modern processors and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs, comprising several processor cores and IP components communicating via a network-onchip (NoC). As a side-effect of this trend, ensuring their correctness has become increasingly problematic. In particular, the networkon-chip often includes complex features and components to support the required communication bandwidth among the nodes in the system. In this landscape, it is no wonder that design errors in the NoC may go undetected and escape into the final silicon, with potential detrimental impact on the overall system.In this work, we propose ForEVeR, a solution that complements the use of formal methods and runtime verification to ensure functional correctness in NoCs. Formal verification, due to its scalability limitations, is used to verify the smaller modules, such as individual router components. We complete the protection against escaped design errors with a runtime technique, a network-level error detection and recovery solution, which monitors the traffic in the NoC and protects it against escaped functional bugs that affect the communication paths in the network. To this end, ForEVeR augments the baseline NoC with a lightweight checker network that alerts destination nodes of incoming packets ahead of time. If a bug is detected, flagged by missed packet arrivals, a recovery mechanism delivers the in-flight data safely to the intended destination via the checker network. ForEVeR's experimental evaluation shows that it can recover from NoC design errors at only 4.8% area cost for an 8x8 mesh interconnect, with a recovery performance cost of less than 30K cycles per functional bug manifestation. Additionally, it incurs no performance overhead in the absence of errors.

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Section: Related Workmentioning

confidence: 99%

Formally enhanced runtime verification to ensure NoC functional correctness

Parikh

Bertacco

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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“…Previous work has also introduced in-circuit assertions via hardware assertion checkers for each assertion in a design. Tools targeted at ASIC design provide assertion checkers using SVA [10], PSL [11], and OVL [12]. Academic tools such as Camera's debugging environment [13] and commercial tools such as Temento's DiaLite also provide assertion checkers for HDL.…”

Section: Related Researchmentioning

confidence: 99%

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Curreri

Stitt

George

2011

International Journal of Reconfigurable Computing

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Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy registertransfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

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“…Later, [4] proposed to synthesize more complex control unit (i.e., assertion checker) to monitor complex behaviors of the CUD (e.g., ATB communication protocol). The unit is a state machine that can be generated from the description with formal languages for assertion-based verification.…”

Section: Trace-based Debug Controlmentioning

confidence: 99%