High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Curreri, John; Stitt, Greg; George, Alan

doi:10.1155/2011/406857

Cited by 19 publications

(10 citation statements)

References 14 publications

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“…Evaluation for HLV was performed on a SHA-1 core obtained from the OpenCores archives were implemented using distributed logic to save BRAM resources for the processor or the Research at the University of Florida (UF) [66,77] investigated an approach to validating designs implemented with high-level synthesis and appears to be the only work devoted to in-circuit validation against a high-level language specification. We were unable to identify any other product-research or commercial-that compared a high-level specification directly with implemented hardware.…”

Section: Resultsmentioning

confidence: 99%

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Iskander

Patterson

Craven

2011

2011 21st International Conference on Field Programmable Logic and Applications

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Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs.The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger.This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.

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Section: Resultsmentioning

confidence: 99%

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Iskander

Patterson

Craven

2011

2011 21st International Conference on Field Programmable Logic and Applications

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“…Another work on embedding synthesizable assertion checkers is done in [26]. The authors used Impulse-C as the system-level design language to represent the DUV and its assertion checkers.…”

Section: Implementing Assertion Checkers On Hardwarementioning

confidence: 99%

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Uchevler

Svarstad

2018

International Journal of Reconfigurable Computing

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With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

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“…Typically, such constructs are supported only by logic simulators or formal verification tools and are discarded for hardware, although researchers have proposed extending these into silicon [4], [11]. Previous approaches, however, insert assertions by modifying the original hardware description and resynthesising the entire circuit -HLS assertions can degrade FPGA performance by 3% [4].…”

Section: Background and Related Workmentioning

confidence: 99%

“…A promising approach uses in-circuit assertions [4] to verify designs at run-time. Because they run in the same circuit as the design under test, in-circuit assertions can run much faster than simulation, allowing testing to be more thorough.…”

Section: Introductionmentioning

confidence: 99%

Transparent In-Circuit Assertions for FPGAs

Hung

Todman

Luk

2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Commonly used in software design, assertions are statements placed into a design to ensure that its behaviour matches that expected by a designer. Although assertions apply equally to hardware design, they are typically supported only for logic simulation, and discarded prior to physical implementation. In this paper, we propose a new HDL-agnostic language for describing latency-insensitive assertions and novel methods to add such assertions transparently to an already placed-androuted circuit without affecting the existing design. We also describe how this language and associated methods can be used to implement semi-transparent exception handling. The key to our work is that by treating hardware assertions and exceptions as being oblivious or less sensitive to latency, assertion logic need only use spare FPGA resources. We use network-flow techniques to route necessary signals to assertions via spare flipflops, eliminating any performance degradation, even on large designs (92% of slices in one test). Experimental evaluation shows zero impact on critical-path delay, even on large benchmarks operating above 200MHz, at the cost of a small power penalty.

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High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Cited by 19 publications

References 14 publications

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Transparent In-Circuit Assertions for FPGAs

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