Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Abstract

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs.The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger.This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.

Accelerating FPGA debug

“…Scan techniques can provide complete visibility into the state of all flip-flops in the design but typically require that the circuit be halted before scan-out. This can greatly slow down their use for real-time debugging; Iskander et al [2011] reported that viewing one flip-flop using device readback can take 2-8 seconds.…”

“…Scan-based techniques involve connecting internal flip-flops sequentially; in FPGAs, this can be achieved using general-purpose soft-logic, as in Wheeler et al [2001], where the area and delay costs can be prohibitive, or through dedicated device readback support [Iskander et al 2011]. Scan techniques can provide complete visibility into the state of all flip-flops in the design but typically require that the circuit be halted before scan-out.…”

Effective FPGA debug for high-level synthesis generated circuits

“…In this work they do not use trace buffers, but rather leverage the device readback feature of certain FPGAs, that allows all registers within the FPGA to be read externally. The major drawbacks of this approach is that it is very slow, requiring several seconds to read values from the FPGA [30], and that it can only be used for a live-stepping flow. In order to perform in-situ debugging, the circuit would need to be started and stopped for each instruction.…”

Trace-based automated logical debugging for high-level synthesis generated circuits

“…Typically it involves selecting a large number of signals, tracing their values concurrently during the execution, and analyzing them to find misbehaviors. To effectively do this, any HW debugging technique needs to provide three main features [2]: 1) signal observability; 2) hardware controllability; 3) limited turnaround times. Signal observability is the ability to see the values of the largest number of signals in the design, with the finest granularity, across the largest time span as possible.…”