Trace-based automated logical debugging for high-level synthesis generated circuits

Abstract

Abstract-In this paper we present an approach for debugging hardware designs generated by High-Level Synthesis (HLS), relieving users from the burden of identifying the signals to trace and from the error-prone task of manually checking the traces. The necessary steps are performed after HLS, independently of it and without affecting the synthesized design. For this reason our methodology should be easily adaptable to any HLS tools.The proposed approach makes full use of HLS compile time informations. The executions of the simulated design and the original C program can be compared, checking if there are discrepancies between values of C variables and signals in the design. The detection is completely automated, that is, it does not need any input but the program itself and the user does not have to know anything about the overall compilation process. The design can be validated on a given set of test cases and the discrepancies are detected by the tool. Relationships between the original high-level source code and the generated HDL are kept by the compiler and shown to the user. The granularity of such discrepancy analysis is per-operation and it includes the temporary variables inserted by the compiler. As a consequence the design can be debugged as is, with no restrictions on optimizations available during HLS.We show how this methodology can be used to identify different kind of bugs: 1) introduced by the HLS tool used for the synthesis; 2) introduced using buggy libraries of hardware components for HLS; 3) undefined behavior bugs in the original high-level source code.

Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis

“…To perform Discrepancy Analysis, we generate control flow traces for every software function and its corresponding FSM in the generated hardware [7]. In software, we instrument the high-level code to dump the identifiers of the basic blocks traversed during execution.…”

“…It automatically compares the actual values with the expected behavior generated in software. Any difference is isolated and back-traced to the high-level source code, automatically identifying the first point of failure [7].…”

“…To debug a HLS-generated IP block, we rely on Discrepancy Analysis (DA) [7], a novel technique for automated bug detection based on the notion of equivalence between the execution of the original source code and the corresponding hardware generated through HLS. The DA flow is depicted in Fig.…”

“…In fact, a component could contain a bug that has not been exercised by functional testing. These errors can be structural or functional [7]. The former include, for example, errors in the hardware resources used to implement operations or in the interconnection between components, and bit flips due to aggressive HLS optimizations.…”

“…Due to the high cost of verification (more than 50% of the overall design time) [6], system designers need automated methodologies to efficiently identify bugs without exposing any intellectual property in open format. We promote an approach that extends Discrepancy Analysis [7], i.e., a state-of-the-art technology for automated bug detection in HLS-generated circuits. Our solution leverages an open-source verification engine used by the system designers to automatically debug the interactions of IP blocks provided by different vendors.…”