Congenic strains of mice susceptible (B10A.Bcgs) or resistant (B10A.Bcgr) to BCG were established. Here we describe the model system which has been established to analyze the functional activities of macrophages in the two strains. We have immortalized bone marrow macrophages from B10A.Bcgs and B10A.Bcgr congenic strains of mice and derived cloned macrophage lines designated B10S and B10R, respectively. B10R and B10S cell lines exhibited surface markers and morphology typical of macrophages. B10S and B10R were similar in their phagocytic activity, in their level of c-fms, in their transforming growth factor beta (TGF beta) mRNAs expression, and in their expression of tumoricidal activity in response to interferon-gamma (IFN gamma) plus lipopolysaccharides (LPS). However, B10R macrophages expressed a higher level of la mRNA when activated with IFN gamma compared with B10S macrophages. Analysis of the bacteriostatic activity of the two cell lines revealed that B10R macrophages were much more active in inhibiting Mycobacterium smegmatis replication than B10S. To measure the intracellular destruction of bacilli, a bactericidal assay based on hybridization with an oligonucleotide probe specific for mycobacterial ribosomal RNA was designed. The results demonstrated that B10R macrophages were endowed with enhanced constitutive bactericidal activity as compared with B10S. In conclusion we have obtained macrophage lines from bone marrow of B10A.Bcgs and B10A.Bcgr mice that express to a similar extent functional and phenotypic characteristics of macrophages. However, we demonstrate that relative to B10S macrophages, the B10R macrophages have higher expression of la mRNA and that they are constitutively more active in expressing mycobactericidal activity.

Assertion-based verification with languages such as PSL is gaining in importance. From assertions, one can generate hardware assertion checkers for use in emulation, simulation acceleration and silicon debug. We present techniques for checker generation of the complete set of PSL properties, including all variants of operators, both strong and weak. A full automata-based approach allows an entire assertion to be represented by a single automaton, hence allowing optimizations that can not be done in a modular approach where subcircuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is derived for other operators. Automata splitting is introduced for an efficient implementation of the eventually! operator.

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Assertion-based verification (ABV) is emerging as a

In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion-Based Verification (ABV) languages. A checker generator capable of transforming assertions into efficient circuits allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms for sequence fusion and length matching intersection, two SERE operators that are not typically used over regular expressions. We also develop an algorithm for generating failure detection automata, a concept critical to extending regular expressions for ABV, as well as present our efficient symbol encoding. Experiments with complex sequences show that our tool outperforms the best known checker generator.

Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertionu to be represented by a single automaton, hence allowing optimizations which can not be done in a modular approach where sub-circuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is developed and applied for all other operators. We show that the generated checkers anre resource-efficient for use in hardwarre emulation, simulation acceleration and silicon debug.

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