Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties

Abstract

Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertionu to be represented by a single automaton, hence allowing optimizations which can not be done in a modular approach where sub-circuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is developed and applied for all other operators. We show that the generated checkers anre resource-efficient for use in hardwarre emulation, simulation acceleration and silicon debug.

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

“…FoCs [35] developed by IBM and MBAC [25][26][27] [57,58,72,79] propose several practical techniques for generating FieldProgrammable Gate Array (FPGA) hardware monitors for Signal Temporal Logic (STL), an extension of MTL handling predicates over the real-values.…”

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation

“…The research on the topic of converting PSL assertions to design representation such as HDL is gaining its popularity. There are several approaches published in recent time [2,3,4,15]. The most widely known tool for this task is FoCs by IBM [5].…”

Symbolic Compilation of PSL

“…Motivated by the needs of dynamic verification, the work in [7] studied how to convert PSL formulas into dynamic checkers, also known as monitors. The goal and the assumptions on the input formula are different from the static verification case.…”