Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation

Jenihhin, Maksim; Raik, Jaan; Chepurov, Anton; Ubar, Raimund

doi:10.1109/ets.2008.22

Cited by 5 publications

(3 citation statements)

References 9 publications

(10 reference statements)

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“…11. For the experimental results, performed in [ 22 ], a set of 5 realistic assertions has been created for each benchmark. The assertions were selected on the following basis:…”

Section: Resultsmentioning

confidence: 99%

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Application of high-level decision diagrams for simulation-based verification tasks

Jenihhin¹,

Raik²,

Chepurov³

et al. 2010

Estonian J. Eng.

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This paper describes the advantages of the application of a system representation model, called High-Level Decision Diagrams (HLDDs), for hardware functional verification. Two tasks of simulation-based verification, considered in this paper, are assertion checking and code coverage analysis. Assertion checking employs temporal extension of an existing HLDD model aimed at supporting temporal properties, expressed in Property Specification Language (PSL). The described approach to code coverage analysis provides for more accurate results than traditional VHDL code coverage methods. Experimental results show the feasibility and efficiency of the HLDDsbased approaches.

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“…11. For the experimental results, performed in [ 22 ], a set of 5 realistic assertions has been created for each benchmark. The assertions were selected on the following basis:…”

Section: Resultsmentioning

confidence: 99%

“…In order to support complex temporal constructs of PSL assertion, an extension for the HLDD modelling formalism has been proposed [ 22 ]. The extension is referred to as temporally extended high-level decision diagrams (THLDDs).…”

Section: Temporally Extended Hlddsmentioning

confidence: 99%

Application of high-level decision diagrams for simulation-based verification tasks

Jenihhin¹,

Raik²,

Chepurov³

et al. 2010

Estonian J. Eng.

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“…During the verification phase they are simulated together with the design and help to discover design's incorrect implementation faster and more efficiently (see [1]) or checked formally. Further, the assertions are removed from the design's synthesizable version.…”

Section: Introductionmentioning

confidence: 99%

On reusability of verification assertions for testing

Jenihhin

Raik

Ubar

et al. 2008

2008 11th International Biennial Baltic Electronics Conference

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Assertions have proven to be an effective mechanism to improve quality and to speed-up simulationbased design verification. They are created and embedded to the simulatable design description by the designer, the person with the deepest knowledge about the desired functionality and its real implementation. In this paper we propose to reuse this valuable information during the design manufacturing testing phase to increase the test quality and efficiency. The paper considers different types of design properties created for verification such as environmental assumptions and internal signal assertions. The reusable information is proposed to be applied for test pattern generation, embedded test observability improvement and DfT (design for testability) enhancement.

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