Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug

Boulé, Marc; Chenard, J.-S.; Žilić, Željko

doi:10.1109/iccd.2006.4380831

Cited by 35 publications

(25 citation statements)

References 8 publications

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“…We have synthesis our experiments on all valid configurations. TABLE I shows that the configuration (1,7,13) is the best configuration for resource usage. For energy consumption, configuration (1,8,11) is the best.…”

Section: Resultsmentioning

confidence: 99%

“…For energy consumption, configuration (1,8,11) is the best. (2,3,28) 28.70 0.21 (1,4,22) 28.50 0.21 (1,5,17) 28.42 0.20 (1,6,15) 28.11 0.20 (1,7,13) 28.02 0.18 (1,8,11) 28.20 0.17 (1,9,10) 28.32 0.20 (1,14,9) 28.40 0.21 (1,15,7) 28.70 0.22 No clustering 29.01 0.32…”

Section: Resultsmentioning

confidence: 99%

“…Then, using MBAC [8] and its rewrite rules [8], we generated Verilog RTL for assertions and added them to the design. Debug enhancements [13], SystemC path [14] and FPGA integration [15] are also available for integration.…”

Section: Resultsmentioning

confidence: 99%

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Enabling efficient post-silicon debug by clustering of hardware-assertions

Neishaburi

Zilic

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the first silicon becomes available. We consider the Assertion Based Verification techniques for the post-silicon debugging based on the insertion of hardware checkers in the debug infrastructure for complex systems on chip. This paper proposes a method to cluster hardware-assertion checkers using the graph partitioning approach. It turns out that having the clusters of hardwareassertions and controlling each cluster selectively during the debug mode and normal operation of the circuit makes integration of assertions inside the circuits easier, and causes lower energy consumption and efficient debug scheduling.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Enabling efficient post-silicon debug by clustering of hardware-assertions

Neishaburi

Zilic

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…Safarpour et al [10] use SAT solving to find circuit locations to automatically detect and repair errors using a stuck-at fault model. There has also been work on developing on-chip monitors for enhancing observability [11], [12], [13]; however, there has been little work on decomposing such monitors into on-chip and off-chip components. De Paula et al [14] use SAT-solving techniques to successively "backspace" from a crashed post-silicon state to provide an execution trace that is used for off-line debugging.…”

Section: Related Workmentioning

confidence: 99%

Connecting pre-silicon and post-silicon verification

Ray

Hunt

2009

2009 Formal Methods in Computer-Aided Design

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Abstract-We present a framework for post-silicon analysis, that provides a formal, bidirectional communication with presilicon verification. We show how to exploit the framework to provide a formal guarantee on post-silicon verification accuracy under limited observability. In particular, we partition a presilicon assertion checker (with full observability) into (1) a limited-observability checker and (2) an in-silicon integrity unit. The composition of the two units is guaranteed to provide the same accuracy as a pre-silicon checker. We apply the framework in the verification of a cache system.

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“…A work-around to this limitation has been to keep these checkers off-platform; however, the overhead of transferring the monitored signal data off the platform severely limits the viability of this work-around. As a result, current industry methodologies have focused on limiting the number of synchronization events between host and platform by: i) accumulating interactions between the design and the testbench into longer and infrequent transactions [13,16], ii) synthesizing the simpler checkers into hardware for simulation alongside the design [3], or iii) recording the values of critical design signals during simulation on-platform and offloading the data at the end to check for consistency with a software checker [6]. Among these solutions, variants of the latter approach are dominant for microprocessor validation on acceleration and emulation platforms.…”

Section: Introductionmentioning

confidence: 99%

ArChiVED: Architectural checking via event digests for high performance validation

Hsu

Chatterjee

Morad

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Simulation-based techniques play a key role in validating the functional correctness of microprocessor designs. A common approach for validating microprocessors (called instruction-by-instruction, or IBI checking) consists of running a RTL and an architectural simulation in lock-step, while comparing processor architectural state at each instruction retirement. This solution, however, cannot be deployed on long regression tests, because of the limited performance of RTL simulators. Acceleration platforms have the performance power to overcome this issue, but are not amenable to the deployment of an IBI checking methodology. Indeed, validation on these platforms requires logging activity on-platform and then checking it against a golden model off-platform. Unfortunately, an IBI checking approach following this paradigm entails a large slowdown for the acceleration platform, because of the sizable amount of data that must be transferred off-platform for comparison against the golden model. In this work we propose a sequence-by-sequence (SBS) checking approach that is efficient and practical for acceleration platforms. Our solution validates the test execution over sequences of instructions (instead of individual ones), thus greatly reducing the amount of data transferred for off-platform checking. We found that SBS checking delivers the same bug-detection accuracy as traditional IBI checking, while reducing the amount of traced data by more than 90%.

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Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug

Cited by 35 publications

References 8 publications

Enabling efficient post-silicon debug by clustering of hardware-assertions

Enabling efficient post-silicon debug by clustering of hardware-assertions

Connecting pre-silicon and post-silicon verification

ArChiVED: Architectural checking via event digests for high performance validation

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