Enabling efficient post-silicon debug by clustering of hardware-assertions

Abstract

Abstract-Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the first silicon becomes available. We consider the Assertion Based Verification techniques for the post-silicon debugging based on the insertion of hardware checkers in the debug infrastructure for complex systems on chip. This paper proposes a method to cluster hardware-assertion checkers using the graph partitioning approach. It turns out that having the clusters of hardwareassertions and controlling each cluster selectively during the debug mode and normal operation of the circuit makes integration of assertions inside the circuits easier, and causes lower energy consumption and efficient debug scheduling.

On a New Mechanism of Trigger Generation for Post-Silicon Debugging

“…Incorporation of assertion checkers as a trigger unit is appealing in scan-based run-stop debug as well as the ELA-based infrastructure [3], [21]. The authors in [21] and [37] investigated a method for clustering assertion checkers inside the design; however, they have not integrated these clusters of checkers inside a trigger unit.…”

“…The authors in [21] and [37] investigated a method for clustering assertion checkers inside the design; however, they have not integrated these clusters of checkers inside a trigger unit. Assertion checkers are considered as a building block in our proposed trigger generation tool.…”

“…Throughout the validation process, the prototypes are connected to specialized validation platforms that facilitate running post-silicon tests, often a mix of directed and constrained-random workloads. Upon completion of each test, the output of the prototype is checked against an architectural simulator, or in some cases, self-checked [1], [2], [4], [9], [10], [21]. When a check fails, indicating the existence of design errors, the post-silicon validation commences, seeking to localize the cause of failures.…”

“…Moreover, realistic corner cases are more likely to be exercised than in simulations, and thus there will be a better opportunity to catch hard-to-detect bugs. Post-silicon validation in general involves four steps: failure detection, failure localization, root cause analysis and, finally, correcting (or bypassing) the problem by patching [21], [24], [31].…”

An infrastructure for debug using clusters of assertion-checkers

“…Moreover, the time-consuming process of identifying the root-causes of failures will be significantly reduced by selectively offloading the related information of the clusters that contain fired assertions. In this paper, we extend the concepts and definitions explored in [6] and provide the implementation details and comprehensive comparison with the previous work. The prior work on post-silicon debugging that centers around the use of assertion-checkers is described in Section 2.…”