Connecting pre-silicon and post-silicon verification

Ray, Sandip; Hunt, Warren A.

doi:10.1109/fmcad.2009.5351128

Cited by 16 publications

(2 citation statements)

References 12 publications

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“…A significant amount of research has focused on detecting and localizing bugs in silicon chips. Several approaches [1], [18], [20] have built hardware on-chip monitors to collect hardware execution traces with internal signals. Assertionbased verification [5], [10] and formal method [6] have been used to analyze and debug the execution traces from onchip monitors.…”

Section: Related Workmentioning

confidence: 99%

Validating direct memory access interfaces with conformance checking

Li¹,

Cong²,

Yang³

et al. 2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Direct Memory Access (DMA) interfaces are a common and important component of Hardware/Software (HW/SW) interfaces between peripheral devices and their device drivers. We present a HW/SW co-validation framework to validate DMA interface implementations of a device and its driver. This framework employs a virtual prototype of the device as a reference model and performs co-validation in two stages: (1) conformance checking which checks the DMA interface conformance between the device and its virtual prototype; (2) property checking which checks device/driver interactions across the DMA interface. In conformance checking, the virtual prototype infers the device state transitions by taking the same driver request sequence to the device. Property checking verifies system properties over the device state transitions exposed through the virtual prototype. This framework assists HW/SW integration validation by detecting DMA interface bugs in both devices and drivers. Furthermore, we have developed three key techniques: capture-on-write policy, partial capture, and environmental input prediction, to address two major challenges in scaling the framework: DMA capture overhead and imprecise environmental input simulation. We have applied this approach to four Ethernet adapters, discovering 12 serious DMA interface bugs from the devices, their virtual prototypes and their drivers. The results demonstrate that our approach has major potential in facilitating HW/SW co-validation.

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Section: Related Workmentioning

confidence: 99%

Validating direct memory access interfaces with conformance checking

Li¹,

Cong²,

Yang³

et al. 2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Several approaches [3,8,12] integrate formal specifications into post-silicon checking of hardware by observing its execution trace. In [14], hardware monitors are introduced to ameliorate observability requirements on silicon. It uses pre-silicon RTL models to construct hardware monitors.…”

Section: Related Workmentioning

confidence: 99%

Post-silicon conformance checking with virtual prototypes

Xie

Cong

2013

Proceedings of the 50th Annual Design Automation Conference

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Virtual prototypes are increasingly used in device/driver co-development and co-validation to enable early driver development and reduce product time-to-market. However, drivers developed over virtual prototypes often do not work readily on silicon devices, since silicon devices often do not conform to virtual prototypes. Therefore, it is important to detect the inconsistences between silicon devices and virtual prototypes.We present an approach to post-silicon conformance checking of a hardware device with its virtual prototype, i.e., a virtual device. The conformance between the silicon and virtual devices is defined over their interface states. This approach symbolically executes the virtual device with the same driver request sequence to the silicon device, and checks if the interface states of the silicon and virtual devices are consistent. Inconsistencies detected indicate potential errors in either the silicon device or the virtual device. We have evaluated our approach on three network adapters and their virtual devices, and found 15 inconsistencies exposing 15 real bugs in total from the silicon and virtual devices. The results demonstrate that our approach is useful and efficient in facilitating device/driver covalidation at the post-silicon stage.

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SoC Instrumentations: Pre-Silicon Preparation for Post-Silicon Readiness

Ray

2018

Post-Silicon Validation and Debug

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Connecting pre-silicon and post-silicon verification

Cited by 16 publications

References 12 publications

Validating direct memory access interfaces with conformance checking

Validating direct memory access interfaces with conformance checking

Post-silicon conformance checking with virtual prototypes

SoC Instrumentations: Pre-Silicon Preparation for Post-Silicon Readiness

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