On signal tracing in post-silicon validation

Xu, Yang; Liu, Ming

doi:10.1109/aspdac.2010.5419883

Cited by 21 publications

(8 citation statements)

References 22 publications

(37 reference statements)

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“…This is due to the fact that we only tap a small portion of the signals in the circuits (9.5% to 20.5%) and hence we will miss the error evidences if the bug propagates to other signals. This is also because the tapped signals in our experiment are randomly selected and the detection quality cannot be guaranteed 4 .…”

Section: Methodsmentioning

confidence: 99%

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On efficient silicon debug with flexible trace interconnection fabric

Liu

2012

2012 IEEE International Test Conference

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Trace-based debug solutions facilitate to eliminate bugs escaped from pre-silicon verification and have gained wide acceptance in the industry. Generally speaking, a number of "key" signals in the circuit are tapped, but not all of them can be observed at the same time due to the limited trace bandwidth. Therefore, a trace interconnection fabric is utilized to output either a subset of signals with multiplexor (MUX) network or compressed signatures with XOR network to the trace memory/port in each debug run. However, both kinds of trace interconnection fabrics have limitations. On one hand, with MUX-based fabric, the visibility of the circuit is limited and it requires many debug runs to locate errors. On the other hand, with XOR-based fabric, typically clean "golden vectors" (i.e, without unknown bits) are required so that signatures are not corrupted. In this paper, we propose a flexible trace interconnection fabric design that is able to overcome the above limitations, at the cost of little extra design-for-debug hardware. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.

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Section: Methodsmentioning

confidence: 99%

“…One effective post-silicon debug technique is to monitor and trace the behaviors of the circuit under debug (CUD) during its normal operation [4]. As shown in [5], for million-gate industrial designs with trace-based debug support, it is common to tap thousands of "key" signals in the circuit.…”

Section: Introductionmentioning

confidence: 99%

On efficient silicon debug with flexible trace interconnection fabric

Liu

2012

2012 IEEE International Test Conference

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“…Silicon debug requires a relatively large engineering effort, accounting for a significant portion of the total time-to-market of the silicon product and this portion has been projected to grow [7,8]. Several design-for-debug solutions have been proposed in the past to provide observability of a circuit's internal signals [63,64,7,65]. Most of these methods are based either on scan dumps or signal tracing.…”

Section: Post-silicon Debug Using Signal Tracingmentioning

confidence: 99%

Test and debug solutions for 3D-stacked integrated circuits

Deutsch

Chakrabarty

2015

2015 IEEE International Test Conference (ITC)

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Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does iv not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. ...

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“…Fig. 1 depicts the general trace-based debug architecture [17]. At design stage, a number of internal signals are selected to be tapped.…”

Section: Preliminaries and Motivationmentioning

confidence: 99%