Formally enhanced runtime verification to ensure NoC functional correctness

Abstract

As silicon technology scales, modern processors and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs, comprising several processor cores and IP components communicating via a network-onchip (NoC). As a side-effect of this trend, ensuring their correctness has become increasingly problematic. In particular, the networkon-chip often includes complex features and components to support the required communication bandwidth among the nodes in the system. In this landscape, it is no wonder that design errors in the NoC may go undetected and escape into the final silicon, with potential detrimental impact on the overall system.In this work, we propose ForEVeR, a solution that complements the use of formal methods and runtime verification to ensure functional correctness in NoCs. Formal verification, due to its scalability limitations, is used to verify the smaller modules, such as individual router components. We complete the protection against escaped design errors with a runtime technique, a network-level error detection and recovery solution, which monitors the traffic in the NoC and protects it against escaped functional bugs that affect the communication paths in the network. To this end, ForEVeR augments the baseline NoC with a lightweight checker network that alerts destination nodes of incoming packets ahead of time. If a bug is detected, flagged by missed packet arrivals, a recovery mechanism delivers the in-flight data safely to the intended destination via the checker network. ForEVeR's experimental evaluation shows that it can recover from NoC design errors at only 4.8% area cost for an 8x8 mesh interconnect, with a recovery performance cost of less than 30K cycles per functional bug manifestation. Additionally, it incurs no performance overhead in the absence of errors.

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

“…Similar number for NoCAlert [14] was 97%, and the technique reached 100% after 28 cycles. The respective numbers for ForEVeR [13] were 30% and 11950 cycles. This gain in the proposed approach was achieved due to the facts that there were checkers devised for arbiter states and that the implemented state encoding was one-hot.…”

A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems

“…Logic/Latch Hardening [18,32] Pipeline Redundancy [14] Monitoring and Correcting model [39,31,29] Hard Faults…”

“…Second, soft errors cannot be recovered by spatial redundancy and their recovery in the End-to-End level is inefficient. The FoReVer framework [29] also presented a network level method to detect and recover from routing errors: lost, duplicated, and misrouted packets. Since FoReVer is based on End-to-End detection and recovery, dealing with soft errors requires retransmission of the whole packet instead of an online recovery.…”

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

“…Prior research [Borrione et al 2007;Parikh and Bertacco 2011] has identified four main conditions that ensure functional correctness within the network: (1) no packets are dropped, (2) delivery time is bounded, (3) no data corruption occurs, and (4) no new packet is generated within the network. These four conditions guarantee functional correctness [Borrione et al 2007;Parikh and Bertacco 2011]. The 32 identified invariances were categorized according to the aforementioned four general requirements, as described in Prodromou et al [2012].…”