Area-efficient architectures for the Viterbi algorithm. I. Theory

Shung, C.B.; Lin, Hong-Da; Cypher, Robert; Siegel, Paul H.; Thapar, H.K.

doi:10.1109/26.223789

Cited by 49 publications

(16 citation statements)

References 13 publications

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“…(14) and (18), i.e., by using the interpretations of P ðiÞ S 2 in Eqs. (13) and (15). The definition of P ðiÞ S 2 in Eq.…”

Section: Square Matrix Transpose Networkmentioning

confidence: 99%

“…Such an approach requires complex write, shift, and read schemes and the system is actually a multi-rate system requiring FIFOs to operate at higher frequency than the sample clock. In [15], a one-dimensional permutation network, which performs arbitrary permutations but only for data in sequential form, is proposed. The stride permutations can be realized also with data format converters proposed in [16].…”

Section: Previous Workmentioning

confidence: 99%

“…This approach results in a decomposition where each 2 q Â 2 q submatrix is first transposed using Eq. (15) and then the remaining steps are performed using Eq. (13).…”

Section: Square Matrix Transpose Networkmentioning

confidence: 99%

See 2 more Smart Citations

Stride Permutation Networks for Array Processors

Jarvinen

Salmela

Sorokin

et al. 2007

J VLSI Sign Process Syst Sign Im

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In several digital signal processing algorithms, computational nodes are organized in consecutive stages and data is reordered between these stages. Parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, a systematic design methodology for stride permutation networks is derived. These permutations are represented with Boolean matrices, which are decomposed and mapped directly onto register-based networks. The resulting networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Since the proposed methodology is systematic, it can be exploited in automated design generation.

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“…(14) and (18), i.e., by using the interpretations of P ðiÞ S 2 in Eqs. (13) and (15). The definition of P ðiÞ S 2 in Eq.…”

Section: Square Matrix Transpose Networkmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

See 1 more Smart Citation

Stride Permutation Networks for Array Processors

Jarvinen

Salmela

Sorokin

et al. 2007

J VLSI Sign Process Syst Sign Im

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show abstract

“…The required routing network for the architecture in Section IV-B belongs to the category known as area-efficient [11] because it is fixed-interconnectioned with bus cross number O(P 2 r 2 ); and evenly routes P r buses to the local memories of the P processors at each time unit. However, the area-efficient concept would be more precise if the processor area, which is mainly determined by the memory size, would be considered.…”

Section: Evaluation Of Design Efficiencymentioning

confidence: 99%

Area-efficient architecture for Fast Fourier transform

Hidalgo

López

Argüello

et al. 1999

IEEE Trans. Circuits Syst. II

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We present an area-efficient parallel architecture that implements the constant-geometry, in-place Fast Fourier Transform. It consists of a specific-purpose processor array interconnected by means of a perfect unshuffle network. For a radix r transform of N = r n data of size D and a column of P = r p processors, each processor has only one local memory of N=rP words of size rD, with only one read port and one write port that, nevertheless, make it possible to read the r inputs of a butterfly and write r intermediate results in each memory cycle. The address generating circuit that permits the in-place implementation is simple and the same for all the local memories. The data flow has been designed to efficiently exploit the pipelining of the processing section with no cycle loss. This architecture reduces the area by almost 50% of other designs with a similar performance.

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“…On the other hand when power and area are major concern then the state serial architecture is used. However, a class of area efficient architectures proposed in [8] uses n SCUs for a trellis with p states, where n < p, and fold the computations of several states onto each SCU. This architecture has been used in many implementations ( [1] and [10]) of reconfigurable channel decoders and is also the one that we use.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture

Rajore

Garga

Jamadagni

et al. 2008

2008 International Conference on Application-Specific Systems, Architectures and Processors

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In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards.

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Area-efficient architectures for the Viterbi algorithm. I. Theory

Cited by 49 publications

References 13 publications

Stride Permutation Networks for Array Processors

Stride Permutation Networks for Array Processors

Area-efficient architecture for Fast Fourier transform

Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture

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