Architecture-specific packing for virtex-5 FPGAs

Ahmed, Taneem; Kundarewich, Paul D.; Anderson, Jason; Taylor, Brad; Aggarwal, Ritesh

doi:10.1145/1344671.1344675

Cited by 19 publications

(21 citation statements)

References 19 publications

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“…All the benchmarks are first mapped to 6-input LUT logic networks by the Berkeley ABC technology mapper [13]. Then, the LUT merge algorithm in [14] is applied to merge pairs of small functions (<4 inputs) into dual-output LUTs. After that, FMD [10] and our IPD are performed separately for comparison.…”

Section: Resultsmentioning

confidence: 99%

In-place decomposition for robustness in FPGA

Lee¹,

Feng²,

He³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The programmable logic block (PLB) in a modern FPGA features a built-in carry chain (or adder) and a decomposable LUT, where such an LUT may be decomposed into two or more smaller LUTs. Leveraging decomposable LUTs and underutilized carry chains, we propose to decompose a logic function in a PLB into two subfunctions and to combine the subfunctions via a carry chain to make the circuit more robust against single-event upsets(SEUs). Note that such decomposition can be implemented using the decomposable LUT and carry chain in the original PLB without changing the PLB-level placement and routing. Therefore, it is an in-place decomposition (IPD) with no area and timing overhead at the PLB level and has an ideal design closure between logic and physical syntheses. For 10 largest combinational MCNC benchmark circuits with a conservative 20% utilization rate for carry chain, IPD improves MTTF (mean time to failure) by 1.43 and 2.70 times respectively, for PLBs similar to those in Xilinx Virtex-5 and Altera Stratix-IV.

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Section: Resultsmentioning

confidence: 99%

In-place decomposition for robustness in FPGA

Lee¹,

Feng²,

He³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…We first identify a gating input, i, to the function f using the approach described in Section III-B. If that is successful, we are left with a 5-variable function, g, that is a factor of f (variable i is factored out) 4 . We then use the same procedure to search for a gating input to g. If such an input to g can be identified, then function f can be realized in the logic element.…”

Section: E Cad Implementationmentioning

confidence: 99%

“…LUTs in Stratix-III offer even more fracture-flexibility and can implement two independent 4-LUTs. From the vendor perspective, while the delay benefits of 6-LUTs are desireable, care has been taken to mitigate under-utilization and achieve high logic density [4]. In this paper, we re-examine the LUT structure and challenge the conventional wisdom that full K-input LUTs are necessary to implement K-variable logic functions in FPGA logic blocks.…”

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confidence: 99%

Raising FPGA Logic Density Through Synthesis-Inspired Architecture

Anderson

Wang

Ravishankar

2012

IEEE Trans. VLSI Syst.

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Abstract-We leverage properties of the logic synthesis netlist to define both a new FPGA logic element (function generator) architecture and an associated technology mapping algorithm that together provide improved logic density. We demonstrate that an "extended" logic element with slightly modified K-input LUTs achieves much of the benefit of an architecture with K+1-input LUTs, while consuming silicon area close to a K-LUT (a K-LUT requires half the area of a K+1-LUT). We introduce the notion of "non-inverting paths" in a circuit's ANDinverter graph (AIG) and show their utility in mapping into the proposed logic element architectures. We propose a general family of logic element architectures, and present results showing that they offer a variety of area/performance trade-offs. One of our key results demonstrates that while circuits mapped to a traditional 5-LUT architecture need 15% more LUTs and have 14% more depth than a 6-LUT architecture, our extended 5-LUT architecture requires only 7% more LUTs and 5% more depth than 6-LUTs, on average. Nearly all of the depth reduction associated with moving from K-input to K+1-input LUTs can be achieved with considerably less area using extended K-LUTs. We further show that 6-LUT optimal mapping depths can be achieved with a small fraction of the LUTs in hardware being 6-LUTs and the remainder being extended 5-LUTs, suggesting that a heterogeneous logic block architecture may prove to be advantageous.

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Section: Introductionmentioning

confidence: 99%

Improving logic density through synthesis-inspired architecture

Anderson

Wang

2009

2009 International Conference on Field Programmable Logic and Applications

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We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved logic density. We demonstrate that an "extended" logic element with slightly modified K-input LUTs achieves much of the benefit of an architecture with K+1-input LUTs, while consuming silicon area close to a K-LUT (a K-LUT requires half the area of a K+1-LUT). We introduce the notion of "non-inverting paths" in a circuit's AND-inverter graph (AIG) and show their utility in mapping into the proposed logic element. Results show that while circuits mapped to a traditional 5-LUT architecture need 14% more LUTs and have 12% more depth than a 6-LUT architecture, our extended 5-LUT architecture requires only 7% more LUTs and 2.5% more depth than 6-LUTs, on average. Nearly all of the depth reduction associated with moving from K-input to K+1-input LUTs can be achieved with considerably less area using extended K-LUTs. We further show that 6-LUT optimal mapping depths can be achieved with a small fraction of the LUTs in hardware being 6-LUTs and the remainder being extended 5-LUTs, suggesting that a heterogeneous logic block architecture may prove to be advantageous.

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Architecture-specific packing for virtex-5 FPGAs

Cited by 19 publications

References 19 publications

In-place decomposition for robustness in FPGA

In-place decomposition for robustness in FPGA

Raising FPGA Logic Density Through Synthesis-Inspired Architecture

Improving logic density through synthesis-inspired architecture

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