Raising FPGA Logic Density Through Synthesis-Inspired Architecture

Abstract

Abstract-We leverage properties of the logic synthesis netlist to define both a new FPGA logic element (function generator) architecture and an associated technology mapping algorithm that together provide improved logic density. We demonstrate that an "extended" logic element with slightly modified K-input LUTs achieves much of the benefit of an architecture with K+1-input LUTs, while consuming silicon area close to a K-LUT (a K-LUT requires half the area of a K+1-LUT). We introduce the notion of "non-inverting paths" in a circuit's ANDinverter graph (AIG) and show their utility in mapping into the proposed logic element architectures. We propose a general family of logic element architectures, and present results showing that they offer a variety of area/performance trade-offs. One of our key results demonstrates that while circuits mapped to a traditional 5-LUT architecture need 15% more LUTs and have 14% more depth than a 6-LUT architecture, our extended 5-LUT architecture requires only 7% more LUTs and 5% more depth than 6-LUTs, on average. Nearly all of the depth reduction associated with moving from K-input to K+1-input LUTs can be achieved with considerably less area using extended K-LUTs. We further show that 6-LUT optimal mapping depths can be achieved with a small fraction of the LUTs in hardware being 6-LUTs and the remainder being extended 5-LUTs, suggesting that a heterogeneous logic block architecture may prove to be advantageous.

Design and Implementation of (72,64) Extended Multibit SEC-DAEC Codes in FPGA

“…FPGAs combine six-input LUTs that can complete a six-input limit or two five-input limits if all information sources are shared. A number of estimations have been proposed to diminish an area use in LUT-based FPGAs [9], [10], with some of them [11], keeping an eye on the multi-yield limits given by a part of these FPGAs. Creators are up 'til now coordinating investigation in this point.…”

An Efficient Technique For Switching Functions Simplification

“…The requirement of efficient multiple input logic synthesis in different fields like automatic control system design, many areas of FPGA design flow [2][3][4], VLSI synthesis [5], the design of BIST, feature reduction [6] and biological logic circuits designing [7]. It is possible to design the same functional combinational circuit with various design styles.…”