In-place decomposition for robustness in FPGA

Abstract

The programmable logic block (PLB) in a modern FPGA features a built-in carry chain (or adder) and a decomposable LUT, where such an LUT may be decomposed into two or more smaller LUTs. Leveraging decomposable LUTs and underutilized carry chains, we propose to decompose a logic function in a PLB into two subfunctions and to combine the subfunctions via a carry chain to make the circuit more robust against single-event upsets(SEUs). Note that such decomposition can be implemented using the decomposable LUT and carry chain in the original PLB without changing the PLB-level placement and routing. Therefore, it is an in-place decomposition (IPD) with no area and timing overhead at the PLB level and has an ideal design closure between logic and physical syntheses. For 10 largest combinational MCNC benchmark circuits with a conservative 20% utilization rate for carry chain, IPD improves MTTF (mean time to failure) by 1.43 and 2.70 times respectively, for PLBs similar to those in Xilinx Virtex-5 and Altera Stratix-IV.

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

“…Using the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs by Berkeley ABC mapper as the baseline, we compare our algorithms with the existing best in-place IPD algorithm [6] for MTTF improvement. MTTF is the counterpart of the failure rate of a chip on the system level, which is the predicted elapsed time to the next failure of a system [15], inversely related to the failure rate of the chip under the same testing platform.…”

“…Cong and Minkovich [5] proposed to choose cuts with more Don't Cares (DCs) during technology mapping. Lee et al [6] proposed an In-Place Decomposition (IPD) algorithm to decompose or duplicate a logic function in a programmable logic block into two subfunctions and to converge the subfunctions via a carry chain within the same block. Note that those techniques [3]- [6] consider SEUs on LUTs only, and their improvements for the reliability on the chip level would be much smaller when interconnects are taken into consideration.…”

“…Besides, IPF algorithms are efficient techniques. They do not demand time-consuming Binary Decision Diagram (BDD), Boolean SATtisfiability (SAT) [3], [4] Integer Linear Programming (ILP) [6], or Set of Pairs of Functions to be Distinguished (SPFD) [7] to search for the functionally equivalent reconfiguration. IPF algorithms do not change LUT level placement and routing.…”

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

“…It explicitly considers the detailed fault behavior on routing elements in a post-layout FPGA application. For example, for MUX-based unidirectional routing, when an SEU occurs on a routing CRAM bit, the manifestation of the fault depends on the signal discrepancy at the faulty MUX and the propagation observability [Krishnaswamy et al 2007;Lee et al 2010] from the faulty MUX to primary outputs. By selectively inverting the logic polarity of the driving LUTs that has higher fault propagation observability, the failure rate from interconnect can be reduced.…”

“…TMR (triple modular redundancy) is a classic technique using redundancy to reduce the fault-induced failures, but is known to have high overhead in area, power and performance. Recently, several logic resynthesis-based techniques have been proposed (e.g., [Hu et al 2008;Feng et al 2009Feng et al , 2011Lee et al 2010;Jose et al 2010;Jing et al 2011a]). They apply different logic masking strategies to reduce failures either in LUT or interconnect and involve minimal overhead in area, power, and performance.…”