On improving at no cost the quality of products built with SRAM-based FPGAs

Abstract

Product or design quality encompasses many aspects. One of them is the robustness with respect to perturbations. This robustness depends on the implementation technology, but can also be improved at design time. This paper is focused on designs implemented in SRAM-based FPGAs that are sensitive to soft errors in the configuration memory. An approach is proposed to increase the dependability with respect to configuration errors, at no cost, by selectively hardening parts of the design. The selection of locally duplicated functions is made so that the protections take advantage of FPGA resources that would not be used by the implemented design. An automated design flow is presented for Xilinx Virtex V devices and fault injection results show that the design dependability may be noticeably enhanced. As an example, more than 40% of the LUTs used to implement a Leon3 Sparc v8 processor can be protected against multiple configuration errors with less than 20% resource overheads at the block level. The final system-level overhead may in many cases be null for a given product, either due to the discrete sizes of available FPGAs or to a different repartition of resource budget between system blocks.

Parity Waterfall method

“…2) LUT Content Faults: Most methods are based on the dual-output LUTs and use the unused parts of the LUTs to mask some faults in the LUTs by duplication [10], [11], [12] or use TMR method [13]. The method presented in [14] maximizes the fault-masking capabilities of a LUT using logic decomposition and restructuring.…”