IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

Abstract

Abstract-SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chiplevel MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm.

IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs

“…All designs enhanced by our IPF algorithm passed the functional equivalent checking by the Berkeley ABC mapper. In terms of failure rate reduction and runtime 4 , we compare our LUT and interconnect analysis-based IPF algorithm with the best known synthesis-based in-place algorithm, namely the IPD algorithm [4], and the two IPF algorithms proposed in our previous work that perform analysis on LUTs only [14].…”

“…The "Critical conf bit" algorithm (shown in Fig. 3) and "Critical output" algorithm are the two IPF algorithms proposed in our previous work that perform analysis on LUT only [14]. The "Critical conf bit" algorithm represents the algorithm that employs SDC bits to mask errors on the most critical configuration bit.…”

Reliability Oriented Selective Triple Modular Redundancy for SRAM-Based FPGAs

“…This paper proposed a don't care bits (DC) based Selective Triple Modular Redundancy (bbSTMR) algorithm, which aims at reducing the area overhead of TMR system while maintaining roughly comparable fault tolerance capability. According to the statistical results of [7], 15% ~ 40% of the configuration bits in LUTs has the characteristics of controllable don't cares, consider of the propagation characteristics of the circuit, the complete don't care bits of some special circuit can even reach 60% [8] . Experiments show that those don't care bits are mostly concentrate in some certain LUTs, on the benefits of this phenomenon, those LUTs boasts more don't care bits are regard as SEU-insensitive LUTs while the remaining are SEU-sensitive.…”

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

“…Recently, several logic resynthesis-based SEU mitigation techniques have been proposed, such as ROSE [Hu et al 2008], IPR [Feng et al 2009], IPD , R2 [Jose et al 2010], IPF [Feng et al 2011], and IPV [Jing et al 2011b], which apply different logic masking strategies to mitigate the fault impact with minimum overhead in area, power, and performance. Applied on non-mission-critical FPGA applications, such as networking and communication, these algorithms can reduce SEU-induced failure rates on an LUT or interconnect significantly.…”

“…TMR (triple modular redundancy) is a classic technique using redundancy to reduce the fault-induced failures, but is known to have high overhead in area, power and performance. Recently, several logic resynthesis-based techniques have been proposed (e.g., [Hu et al 2008;Feng et al 2009Feng et al , 2011Lee et al 2010;Jose et al 2010;Jing et al 2011a]). They apply different logic masking strategies to reduce failures either in LUT or interconnect and involve minimal overhead in area, power, and performance.…”