This paper presents a novel fault diagnosis method which overcomes the shortcomings of traditional approaches. It uses dynamic fault tree model for reliability analysis. All minimal cut sequences are generated via a new modular method, while the diagnostic importance factor (DIF) of components and minimal cut sequences are calculated using discrete-time Bayesian network. Also, we introduce the cost of diagnostic importance factor (CDIF) for components to evaluate the influences of the test costs, and combine it with minimal cut sequences’ DIF to determine the order of the system diagnosis. Finally, an example is given to demonstrate the effectiveness of this method.
This paper presents an improved approach to Triple Modular Redundancy (TMR) which concerns don’ t care bits of LUT configuration bits and hence classifies the set of LUTs into SEU-sensitive and SEU-insensitive. Unlike the full TMR approach, the improved approach only triplicates SEU-sensitive LUTs and can greatly reduces the area overhead while maintaining the circuit reliability. The proposed approach is thoroughly tested on the MCNC’91 benchmarks. Compare with the full TMR method the proposed scheme can reduce the area overhead by 26.6% on average, at the same time the circuit reliability only reduced by 9.1 %. The improved approach can also increase mean time between failures (MTBF) by an average of six times more than the original circuit.
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