Analytical unified threshold voltage model of short-channel FinFETs and implementation

Fasarakis, N.; Tsormpatzoglou, A.; Tassis, D. H.; Dimitriadis, C. A.; Papathanasiou, K.; Jomaah, J.; Ghibaudo, G.

doi:10.1016/j.sse.2011.06.049

Cited by 36 publications

(15 citation statements)

References 24 publications

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“…where ϕ (x c , y m ) is the channel potential at the conductive path x c and the position y m of the minimum potential, which shows weak dependence on the gate voltage in the subthreshold region [21], V th is the thermal voltage, and n i is the intrinsic carrier concentration of silicon. The potential at the conductive path ϕ(x c , y m ) can be written as [19] ϕ(x c ,…”

Section: Discussion On the Threshold Voltage Modelmentioning

confidence: 99%

“…2 shows the dependence of the front-gate threshold voltage V tf on the back-gate bias V gb . The values of V tf calculated from the model are compared with the experimental values extracted from the transconductance linear extrapolation method [21], as both values are determined at the onset of inversion. The impact of the back-gate bias on the location of the effective conductive path x c has been modeled with the empirical relations…”

Section: Discussion On the Threshold Voltage Modelmentioning

confidence: 99%

See 1 more Smart Citation

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Karatsori

Tsormpatzoglou

Theodorou

et al. 2015

IEEE Trans. Electron Devices

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An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from −3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools. Index Terms-Back-gate control, compact model, fully depleted silicon-on-insulator (FD-SOI) ultrathin-body and box (UTBB) MOSFETs. 0018-9383

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Section: Discussion On the Threshold Voltage Modelmentioning

confidence: 99%

Section: Discussion On the Threshold Voltage Modelmentioning

confidence: 99%

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Karatsori

Tsormpatzoglou

Theodorou

et al. 2015

IEEE Trans. Electron Devices

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“…The device model used for the simulations is based on the work published in [6][7][8] for the drain current I ds and the internal trans-capacitances C xy of Triple Gate FinFETs. In order to execute the algorithm flow of the proposed tool, the FinFET device model is implemented in Matlab.…”

Section: A Aging Analysis Of the Cmos Invertermentioning

confidence: 99%

“…The device [6][7][8] and HC degradation models [3,4] along with the algorithm that implements the reliability analysis are coded in Matlab.…”

Section: Introductionmentioning

confidence: 99%

A software tool for aging analysis of the CMOS inverter based on hot carrier degradation modeling

Messaris

Goudos

Nikolaidis

et al. 2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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It has been made clear that the presence of hot carriers triggers a series of physical processes that affects the FD-SOI and FinFET device characteristics under normal circuit operation. These effects cumulatively build up over prolonged periods, causing the circuit to age with time, resulting in performance degradations that may eventually lead to circuit failure. In this paper we tackle with the HC effects using a software tool that is able to quantify the HC induced degradation of the devices in a design, and furthermore predict the lifetime of the corresponding circuit. We present the Graphical User Interface (GUI) and we give examples of tool operation.

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“…Whereas several analytical approaches have been developed for the calculation of the potential distribution within the channel [7]- [11], most of the published work on drain current modeling in short-or long-channel FinFETs is limited to double-gate (DG) devices [12]- [16]. Recently, we have proposed a compact and analytical drain current model suitable to nanoscale DG and TG FinFETs [17], [18]. However, this drain current model has to be completed with a compact capacitance-voltage (C-(V ) model, to Manuscript make it suitable for implementation in a SPICE simulator for circuit design and performance exploitation.…”

Section: Introductionmentioning

confidence: 99%

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

Fasarakis

Tsormpatzoglou

Tassis

et al. 2012

IEEE Trans. Electron Devices

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A charge-based compact capacitance model has been developed describing the capacitance-voltage characteristics of undoped or lightly doped ultra-scaled triple-gate fin field-effect transistors. Based on a unified expression for the drain current and the inversion sheet charge density, i.e., the Ward-Dutton linear-charge-partition method and the drain current continuity principle, all trans-capacitances are analytically derived. The developed capacitance model is valid in all regions of operation, from the subthreshold region to the strong inversion region and from the linear region to the saturation region. The gate and source transcapacitances have been validated by 3-D numerical simulations over a large range of device dimensions. The parameters of the capacitance model can be used to accurately predict the transfer and output characteristics of the transistors, making this compact model very useful for circuit designers.

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Analytical unified threshold voltage model of short-channel FinFETs and implementation

Cited by 36 publications

References 24 publications

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

A software tool for aging analysis of the CMOS inverter based on hot carrier degradation modeling

Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs

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