Analytical predictive modeling for the study of the scalability limits of multiple gate MOSFETs

An approach based on particle swarm computation to study the electron mobility in wurtzite GaN

“…The advantages advocated for DG MOSFET, shown in Figure 1 include: ideal subthreshold slope; light doping of the channel reducing the mobility degradation due to the elimination of impurity scattering; good control of short channel effects; ideal subthreshold swing due to the elimination of substrate doping; etc [1][2][3][4]. Previous works which studied the DG MOSFETs include the fabrication procedures, numerical and analytical modeling [1][2][3][4][5][6]. To extract information accurately about the current-voltage (I-V) characteristics require the solution of Schrödinger and Poisson equations based on the non-equilibrium Green's function (NEGF) formalism, assuming quantum effects are to be fully accounted [7].…”

“…But from the nanoscale CMOS circuits design point of view even 2-D solution of numerical NEGF is an overkill approach in term of both complexity and computational cost [7]. For analytical devices modeling, in general, it is difficult or almost impossible to obtain closed analytical models form for nanoscale DG MOSFETs, where this approach requires several approximations during the model development [3,6,8]. Thus, models are obtained by a simplification of the full physical model (quantum effects, short-channel-effects, etc.).…”

Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

“…FinFET devices have been proposed as promising alternatives for the traditional CMOS devices at the nanoscale technologies 2,3 since they have outstanding properties such as improved channel controllability, 4,5 higher I on /I off current ratio, 6 reduced short-channel e®ects, 7 and higher immunity to gate line-edge roughness. 8 Additionally, the near-ideal subthreshold behavior clari¯es the potential usage of FinFET circuits in the near threshold supply voltage regime, which consumes much less energy than the conventional strong-inversion circuits that operate in the superthreshold supply voltage regime.…”

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

“…hort channel effects (SCEs) and process variations are great challenges facing CMOS technology that leads to searching for emerging devices like FinFET and CNFET [1]. FinFET has a promising future to keep on the technology scaling trend for future generations of beyond 22 nm technologies [2].…”