Analytical model for failure rate prediction due to anomalous charge loss of flash memories

Degraeve, R.; Schuler, F.; Lorenzini, Marilinda; Wellekens, D.; Hendrickx, Paul; Houdt, J. Van; Haspeslagh, L.; Groeseneken, G.; Tempel, G.

doi:10.1109/iedm.2001.979607

Cited by 37 publications

(9 citation statements)

References 2 publications

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“…At low defect densities, a one-to-one correlation would be expected. At high defect densities (and this may be the range studied here), it is possible that tunneling through multiple defects may further enhance the TAT process [15,16]. If this applies, the interpretation of the activation energy, E a , may differ from what is proposed above.…”

Section: Defect Creation and Correlation Between Silc Formation Anmentioning

confidence: 70%

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Cartier

Kerber

2009

2009 IEEE International Reliability Physics Symposium

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The stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2 /TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO 2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, E a ~ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (V t ) instability ΔI g /I g ~ dV t 3 . Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and V t -degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO 2 defects -such as oxygen vacancy -and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the V t instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.

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Section: Defect Creation and Correlation Between Silc Formation Anmentioning

confidence: 70%

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Cartier

Kerber

2009

2009 IEEE International Reliability Physics Symposium

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“…9nm for future generations. Scaling the tunnel oxide would lead to anomalous charge leakage, caused by one or two defects in the oxide [2]. Discrete charge storage bypasses this problem, hence allowing for scaling of the tunnel oxide and program/erase voltages.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characterisation of Silicon-Rich-Oxide Based Memory Cells Using Pulsed Current-Voltage Techniques

Rosmeulen

Sleeckx

Meyer

2002

32nd European Solid-State Device Research Conference

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MOS FET's and capacitors with a gate oxide containing a Silicon-Rich-Oxide (SRO) layer were fabricated. Memory action occurs through trapping of charge in the SRO-layer. Pulsed Current-Voltage techniques recording Id-Vg and C-V-curves have been used to determine the cell characteristics. Programming and erasing can be achieved by applying ±8V pulses with 100ms pulse width. Faster programming and HUDVLQJ FDQ EH REWDLQHG E\ DSSO\LQJ HJ V pulses on the gate electrode. The cells have an endurance of 10 5 cycles and an estimated retention of 10 years.

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“…Although a theoretical limit of 4-5 nm tunnel oxide is imposed by the onset of the direct tunneling regime, anomalous charge loss on large memory arrays 2) requires the oxide to be thicker than 7-8 nm in order to guarantee 10 years of retention. To further improve its performance in terms of programming speed and/or decrease of the operating voltages, new concepts are required.…”

Section: Introductionmentioning

confidence: 99%

Enhanced Tunneling Current Effect for Nonvolatile Memory Applications

Govoreanu

Blomme

Houdt

et al. 2003

Jpn. J. Appl. Phys.

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High-k insulators are currently considered for SiO 2 replacement as gate dielectrics in sub-100 nm complementary metaloxide-semiconductor (CMOS) technology nodes. The use of double-layer high-k stacks as tunnel dielectrics could bring important benefits in the nonvolatile memory operation by either reducing the operating voltages and/or increasing the programming speed. In this paper, the influence of the high-k parameters on the tunneling current and requirements for achieving higher programming speed without compromising retention are discussed. We show that enhancement of the tunneling current is possible with two-layer low-k/high-k dielectric stacks and confirm the theoretical results based on our experimental data.

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Analytical model for failure rate prediction due to anomalous charge loss of flash memories

Cited by 37 publications

References 2 publications

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Electrical Characterisation of Silicon-Rich-Oxide Based Memory Cells Using Pulsed Current-Voltage Techniques

Enhanced Tunneling Current Effect for Nonvolatile Memory Applications

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