Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Abstract

The stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2 /TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO 2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, E a ~ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (V t ) instability ΔI g /I g ~ dV t 3 . Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and V t -degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO 2 defects -such as oxygen vacancy -and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the V t instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.

Time dependent dielectric breakdown and stress induced leakage current characteristics of 8Å EOT HfO<inf>2</inf> N-MOSFETS

“…In this case we see a strong dependence of the SILC generation rate on voltage (fig 5a) and indeed temperature (fig. 5b) which disagrees with the model proposed in [12]. However, even the gentlest stress in the single trap regime only yields a SILC generation rate of 0.32 which cannot explain the TDDB results and so an increased bulk HfO 2 trap generation rate seems unlikely.…”

“…There still exists in the literature some confusion over whether SILC is mediated through empty states or if a site needs to trap a carrier to enable it to become involved in the SILC process [12]. In this work the thickness of the layers is such that one would not expect significant trapping, though the SILC component still remains after the discharge indicating that it is mediated through neutral electron traps.…”

Insight Into Electron Traps and Their Energy Distribution Under Positive Bias Temperature Stress and Hot Carrier Aging

“…Application of metal gate/HK stack, however, has increased positive bias temperature instability (PBTI) [1][2][3][4][5][6][7][8]. PBTI originates from electron traps (ETs) and one of their sources is water/hydrogen related species [9,10].…”

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

“…6 shows the band diagram of an NMOS under inversion mode and the components of gate leakage currents. There are three major components of gate leakage [30]:…”

“…The actual reason behind the SILC is a controversial issue. While some groups attribute the SILC phenomenon to the defect generation in the HK layers [30,34,35], others explain SILC by defect generation only in the IL layer [27,36]. J. Yang, et al [13] argued that SILC is caused by defects in both HK and IL layers but mostly dominated by the defects in the IL layer since they have much lower relaxation energy.…”