Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Abstract

Abstract-Bias Temperature Instability (BTI) is a majorreliability concern in CMOS technology, especially with High dielectric constant (High-κ/HK) metal gate (MG) transistors. In addition, the time independent process induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in the BTI degradation. Since time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time zero variability on all these effects simultaneously.To that effect, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000 nm 2 ) in 30nm technology, we observe significant effect of Random Dopant Fluctuation (RDF) on BTI induced variability (σ ΔVth ). In addition, the circuit analysis reveals similar trend on the performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on V th degradation cannot be disregarded in scaled technology and needs to be considered for variation tolerant circuit design.

Enhanced Electrical Properties of Atomic Layer Deposited LaxAlyO Thin Films with Stress Relieved Preoxide Pretreatment

“…In the TDDB measurement, SBD has been reported to be closely dependent on the quality of interfacial layer [33]. Starting with the formation of multi unstable localized conduction paths in the interfacial layer, the gate stack does not breakdown completely in the SBD region.…”

Assessment of BTI‐induced deterioration in vacuum based undoped structure

“…Therefore, one should be careful in choosing proper value of $$$ {V}_{GS} $$$. The value of $$$ {V}_{GS} $$$ should be such that the degradation due to time dependent dielectric breakdown (TDDB) is negligible as compared to BTI 20 . Further, stress conditions for BTI lie below 6 mV/cm electric field across gate oxide and in the temperature range $$$ 100-{250}^{\mathrm{o}}\mathrm{C} $$$.…”

“…The value of V GS should be such that the degradation due to time dependent dielectric breakdown (TDDB) is negligible as compared to BTI. 20 Further, stress conditions for BTI lie below 6 mV/cm electric field across gate oxide and in the temperature range 100 À 250 o C. The high electric field can increase the probability of impact ionization and cause additional degradation due to the hot carrier (HC), this situation can be avoided by choosing an appropriate V GS. 21 For the above consideration, we have biased both gates by 1:9V for NBTI investigation in p-type DGDLJLFET and À1:9 V for PBTI investigation in n-type DGDLJLFET and the rest of the terminals are grounded, as shown in Figure 2.…”