32nd European Solid-State Device Research Conference 2002
DOI: 10.1109/essderc.2002.194970
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Electrical Characterisation of Silicon-Rich-Oxide Based Memory Cells Using Pulsed Current-Voltage Techniques

Abstract: MOS FET's and capacitors with a gate oxide containing a Silicon-Rich-Oxide (SRO) layer were fabricated. Memory action occurs through trapping of charge in the SRO-layer. Pulsed Current-Voltage techniques recording Id-Vg and C-V-curves have been used to determine the cell characteristics. Programming and erasing can be achieved by applying ±8V pulses with 100ms pulse width. Faster programming and HUDVLQJ FDQ EH REWDLQHG E\ DSSO\LQJ HJ V pulses on the gate electrode. The cells have an endurance of 10 5 cycles an… Show more

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Cited by 18 publications
(6 citation statements)
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“…To this aim, the development of investigation techniques, which are able to reduce the impact of charge trapping on measurement results, is a major concern, achieving an increasing interest [2,3]. In this work, we characterize charge trapping in SiO 2 /Al 2 O 3 stacks, making use of a pulsed capacitance-voltage (C-V) technique [4], which allows us to measure a complete C-V characteristic in a relatively short time. This reduces the impact of charge trapping on the measurement results, as opposed to the conventional high-frequency C-V measurement.…”
Section: Introductionmentioning
confidence: 99%
“…To this aim, the development of investigation techniques, which are able to reduce the impact of charge trapping on measurement results, is a major concern, achieving an increasing interest [2,3]. In this work, we characterize charge trapping in SiO 2 /Al 2 O 3 stacks, making use of a pulsed capacitance-voltage (C-V) technique [4], which allows us to measure a complete C-V characteristic in a relatively short time. This reduces the impact of charge trapping on the measurement results, as opposed to the conventional high-frequency C-V measurement.…”
Section: Introductionmentioning
confidence: 99%
“…Arguably, the conventional and off-site radiation response measurements may underestimate the degradation of MOS devices. It was found that the defects in HfO 2 would induce charging and neutralization behaviors during the applied pulse waveform [11]. Therefore, the pulse CV technique is convincing for observing the charge trapping behaviors in relatively short time, which is close to the actual conditions.…”
Section: Introductionmentioning
confidence: 68%
“…It is found that the current component around 7 mA/cm 2 at both the rising and falling edges results from the tunnel oxide capacitive charging/discharging (ICtox). The ICtox current during the voltage pulse (Vpulse) ramping down peaks at around 3 ms, corresponding to the transition point between the electron and hole current injection [11], [12], as the polarity at the storage node switches from positive to negative. Also, as one would expect, the current peaks at 20 mA/cm 2 due to the tunneling current through the tunnel oxide (IRtox), which will not appear until the electrical field across the tunnel oxide is high enough that the Fowler-Nordheim tunneling begins.…”
Section: Resultsmentioning
confidence: 99%