Enhanced Tunneling Current Effect for Nonvolatile Memory Applications

Abstract

High-k insulators are currently considered for SiO 2 replacement as gate dielectrics in sub-100 nm complementary metaloxide-semiconductor (CMOS) technology nodes. The use of double-layer high-k stacks as tunnel dielectrics could bring important benefits in the nonvolatile memory operation by either reducing the operating voltages and/or increasing the programming speed. In this paper, the influence of the high-k parameters on the tunneling current and requirements for achieving higher programming speed without compromising retention are discussed. We show that enhancement of the tunneling current is possible with two-layer low-k/high-k dielectric stacks and confirm the theoretical results based on our experimental data.

The Flash Memory Cell for the Nodes to Come: Material Requirements from a Device Perspective

“…18). Furthermore, a suitable band offset misalignment between the low-k and the high-k layers allows for a substantial enhancement of the current under applied bias [23], due to direct tunneling through a thin (low-k) dielectric layer, resulting in an overall steeper IV tunnel barrier characteristic, compared to that of a single-layer low-k tunnel dielectric of identical electrical thickness. The low-k layer can be implemented (for obvious reasons) in SiO 2 and optimal VARIOT characteristics may be achieved for bottom SiO 2 layers in the stack of 1-2 nm (Fig.…”

Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

“…Since the Al 2 O 3 layer has a lower barrier height, the barrier of the multilayer tunneling oxide is more transparent for injected electrons than that of SiO 2 layer with identical effective thickness (EOT) during the programming operation. Therefore, programming speed can be obviously enhanced by adopting multilayer tunneling oxide [10]. Fig.…”

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

“…In this work, four different high-k materials (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) were explored using the DQT model as these materials can be deposited on SiO 2 layer. [22][23][24] After these matters were clarified, the optimization was performed based on proposed method by Verma et al 14) For simplicity, the optimization was conducted using MOS capacitor (MOS-Cap) structure, in which to fairly assess the electrical behavior of the VARIOT combinations. The equivalent oxide thickness (EOT) of asymmetric VARIOT is fixed for 4 : 1 : 8 nm while varying its low-k thickness, Tox from 1 nm to the corresponding EOT.…”

“…In contrast to the former case, here, the FN tunneling has lower gate voltage at program constraint due to the high barrier of Al 2 O 3 . Although it is known that increasing the barrier of high-k dielectric in VARIOT will only increase the transition voltage from two-layer to one-layer tunneling, 22) its high permittivity has caused high electron tunneling for high gate current as it reaches the FN tunneling regime and saturated at program constraint due to the unchanged gate electrostatic control. Even though the minimum program voltage in all VARIOT combinations was found to be at T ox = 2 nm, it is still yet to be optimized and may or may not be at T ox = 2 nm.…”