Analytic model of endurance degradation and its practical applications for operation scheme optimization in metal oxide based RRAM

Huang, Peng; Chen, B.; Wang, Y. J.; Zhang, F. F.; Shen, Lei; Liu, R.; Zeng, Lang; Du, Gang; Zhang, X.; Gao, Bin; Kang, Jinfeng; Liu, X. Y.; Wang, X. P.; Weng, B. B.; Yan, Tie; Lo, G. Q.; Kwong, Dim‐Lee

doi:10.1109/iedm.2013.6724685

Cited by 49 publications

(33 citation statements)

References 5 publications

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“…In this case, adding a second transistor in series with the RRAM device to limit the maximum current during the negative reset can extend the endurance [20]. Also, note that, by optimizing the set and reset voltages, the endurance degradation can be postponed, and the number of cycles can get extended in a few orders of magnitude as reported in [21]. N everthel ess, the degraded device cannot recover unlimited number of times because the O 2would be consumed during the device operation, and the conductive filament cannot be successfully ruptured by Vo and O 2recombination.…”

Section: Endurance Degradationmentioning

confidence: 99%

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Pouyan

Amat

Rubio

2018

IEEE Trans. Emerg. Topics Comput.

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Among the emerging technologies and devices for highly scalable and low power memory architectures, memristors are considered as one of the most favorable alternatives for next generation memory technologies. They are attracting great attention recently, due to their many appealing characteristics such as non-volatility and compatibility with CMOS fabrication process. But beside all memristor advantages, their drawbacks including manufacturing process variability and limited read/write endurance, could risk their future utilization. This paper will evaluate the impact of reliability concerns in lifetime of memristive crossbars and will present the design basis of two proposed reconfiguration approaches in memristive crossbarbased memories, in order to extend the system lifetime by utilizing available resources in an intense way and without need of failure recovery. It is observed that the adaptive reconfiguring approach can improve the crossbar reliability and extend its lifetime up to 65% in comparison with non-adaptive reconfiguration strategy.

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Section: Endurance Degradationmentioning

confidence: 99%

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Pouyan

Amat

Rubio

2018

IEEE Trans. Emerg. Topics Comput.

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“…Two types of redox RAM endurance degradation . [Colour figure can be viewed at wileyonlinelibrary.com]…”

Section: Reliabilitymentioning

confidence: 99%

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

Vatajelu

Pouyan

Hamdioui

2017

Circuit Theory & Apps

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Summary The power and reliability issues of today's memories (static and dynamic RAMs) reduce the advances achieved by their implementation in scaled technology. There are several emergent memory technologies that address the technical constraints of today's memories, among which the most promising solutions are the resistance‐based memories, such as phase change memories, the redox‐based resistive memories, and the spin‐transfer torque magnetic memories. These technologies are facing various challenges that have to be addressed to render them efficient in today's applications. Until recently, research focus was on the design for performance and power efficiency, but lately, the test and reliability issues of these devices have become of major concern to the community. This paper presents an overview of the challenges and proposed test and reliability boost solutions developed to suit the needs of the emerging memories under analysis. It underlines (1) the unique faults that occur in the memory cell due to known issues in the emerging storage devices, (2) the dedicated solutions developed for efficient testing of the emerging memories under study, (3) the main reliability concerns related to the emerging storage devices, and (4) the design solutions targeted at mitigating these reliability issues. Copyright © 2017 John Wiley & Sons, Ltd.

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“…In the same manner, the device endurance strongly depends on the writing voltage characteristics [13], [14]. The use of a scheme able to guarantee the memory block operations does not ensure an optimal endurance for the devices and may cut back the useful lifetime.…”

Section: Low Resistive State (Lrs) and A High Resistive State (Hrs)mentioning

confidence: 99%

“…The second non-desired effect, derived from the use of larger voltages, is thoroughly described in [13]. There, the device endurance (number of consecutive SET-RESET that a single device supports with no HRS/LRS ratio serious degradation) is studied and modeled.…”

Section: B Lifetime Reductionmentioning

confidence: 99%

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

García‐Redondo

Royer

López‐Vallejo

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-Resistive switching memories (RRAM) are an attractive alternative to non-volatile storage and non-conventional computing systems, but their behavior strongly depends on the cell features, driver circuit and working conditions. In particular, the circuit temperature and the writing voltage scheme become critical issues, determining resistive switching memories performance. These dependencies usually force a design time trade-off among reliability, device endurance and power consumption, and therefore imposing non-flexible functioning schemes and limiting the system performance. In this paper we present a writing architecture that ensures the correct operation no matter the working temperature, and allows the dynamic load of application oriented writing profiles. Thus, taking advantage of more efficient configurations, the system can be dynamically adapted to overcome RRAM intrinsic challenges. Several profiles are analyzed regarding power consumption, temperature-variations protection and operation speed, showing speed-ups near to 700 x compared against other published drivers.

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Analytic model of endurance degradation and its practical applications for operation scheme optimization in metal oxide based RRAM

Cited by 49 publications

References 5 publications

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

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