Analysis of energy efficient PTL based full adders using different nanometer technologies

Abstract

Full adder can be designed using CMOS logic, transmission gates, dynamic logic or pass transistor logic. This paper presents Pass Transistor Logic based one bit full adders. The PTL based adder designs considered were SERF adder, 9A adder, 13A adder, CLRCL adder and 8T adder. Conventional 28T CMOS adder was also analysed. All the designs were simulated using Tanner EDA tool. Simulations were done at 180nm, 130nm and 90nm technologies. Transient analyses were done at frequencies ranging from 100MHz to 500MHz. The load capacitance was varied between 50fF to 250fF. Performance analyses were done with respect to power, delay and energy consumption obtained at 180nm, 130nm and 90nm technologies. At 180nm and 90nm, the 8T adder has lower power delay product (PDP). At 130nm 13A adder has got lower PDP when compared to all other adder designs. The 2bit, 4-bit and 8-bit ripple carry adders were designed at 180nm technology to analyse the performance in real time applications. 8T and 13A ripple carry adders were found to be the best with respect to delay and energy consumption respectively.

Design of power efficient stable 1-bit full adder circuit

“…2T XOR gate based full adder using Gate Diffusion Input (GDI) technique has been proposed [6] to optimize the circuit performance. Full adder can be designed using CMOS logic, transmission gates, dynamic logic or pass transistor logic [7]. All-ntype ripple-carry adder was proposed with low leakage for IoT devices [8].…”

Delay Analysis of Half Subtractor using CMOS and Pass Transistor Logic

“…The PTL based technique uses less number of transistors compared to all other design techniques [10,11].…”