Analysis of CNTFET physical compact model

Maneux, Cristell; Goguet, Johnny; Fregonèse, Sébastien; Zimmer, Thomas; d'Honincthun, H. Cazin; Galdin‐Retailleau, S.

doi:10.1109/dtis.2006.1708733

Cited by 29 publications

(3 citation statements)

References 18 publications

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“…The source–drain bias ( V DS ) is what causes the difference between E FS (Fermi energy of the source) and E FD (Fermi energy of the drain). After integrating all of the energy sub-bands, the I DS can be written as where e is the electron’s charge, k B is the Boltzmann constant, h is the Planck constant, Δ p is the p th energy sub-band, and T is the temperature.…”

Section: Resultsmentioning

confidence: 99%

Use of Ambipolar Dual-Gate Carbon Nanotube Field-Effect Transistor to Configure Exclusive-OR Gate

et al. 2022

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As the physical scaling limit of silicon-based integrated circuits is approached, new materials and device structures become necessary. The exclusive-OR (XOR) gate is a basic logic gate performed as a building block for digital adder and encrypted circuits. Here, we suggest that using the ambipolar property of carbon nanotubes and the threshold modulation ability of dual-gate field-effect transistors, an XOR gate can be constructed in only one transistor. For a traditional XOR gate, 4 to 6 transistors are needed, and this low-footprint topology could be employed in the future for hyperscaling and three-dimensional logic and memory transistor integration.

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Section: Resultsmentioning

confidence: 99%

Use of Ambipolar Dual-Gate Carbon Nanotube Field-Effect Transistor to Configure Exclusive-OR Gate

et al. 2022

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“…A simple model for ballistic nanotransitors is described in [11,12]. For details about this model, we refer the reader to [13][14][15]. In this model, the gate voltage V gs induces charge in the CNTFET channel Q cnt .…”

Section: Approachmentioning

confidence: 99%

Improving the RF Performance of Carbon Nanotube Field Effect Transistor

Hamieh

2012

Journal of Nanomaterials

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Compact model of single-walled semiconducting carbon nanotube field-effect transistors (CNTFETs) implementing the calculation of energy conduction subband minima under VHDLAMS simulator is used to explore the high-frequency performance potential of CNTFET. The cutoff frequency expected for a MOSFET-like CNTFET is well below the performance limit, due to the large parasitic capacitance between electrodes. We show that using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance.

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“…It is a surface potential-based SPICE model simulating CNTs with ballistic conduction behavior. The other compact model used here comes from IMS [4], with the description of the total charge on the nanotube. It explores the DC as well as the dynamical characteristics of the CNTFET.…”

Section: B Nano-componentsmentioning

confidence: 99%

Architecture of neural synaptic array, design and simulation

He¹,

Klein²,

Belhaire³

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

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In this paper, we present the design of artificial neural network architecture to implement the Look-Up Table of reconfigurable circuits. The various cells of schematic used only the carbon nanotubes semiconductors (CNTFET), and the non volatile multi-level resistance. The compatibility between CNTFET and non volatile multi-level resistance in the state of the art has been studied. Then the electrical circuit simulation results demonstrate successful learning of the linearly separable logical functions.

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Analysis of CNTFET physical compact model

Cited by 29 publications

References 18 publications

Use of Ambipolar Dual-Gate Carbon Nanotube Field-Effect Transistor to Configure Exclusive-OR Gate

Use of Ambipolar Dual-Gate Carbon Nanotube Field-Effect Transistor to Configure Exclusive-OR Gate

Improving the RF Performance of Carbon Nanotube Field Effect Transistor

Architecture of neural synaptic array, design and simulation

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